Circuit arrangement for an electric melting furnace

Claim 2

A circuit arrangement for use with an electric melting furnace comprising: a controlled converter for supplying said furnace, said converter including a number of thyristors; a control apparatus for controlling the signal being supplied by said converter including: a control unit connected to said converter; and a current regulator for feeding said control unit, said regulator comprising a feedback path comprising ohmic resistance means; a monitoring circuit for generating at least one indicating signal indicative of the operational state of each of said thyristors; and control switch means responsive to said indicating signal for selectively short-circuiting portions of said resistance means.

Claim 3

A circuit arrangement in accordance with claim 1 in which: said resistance means includes a first resistor which forms a portion of said resistance means; said thyristors are grouped in a single group; said monitoring circuit generates a first signal indicative of the operational state of the thyristors in said single group; and said control switch means responds to said first signal by selectively short-circuiting said first resistor.

Claim 4

A circuit arrangement in accordance with claim 1, in which: said resistance means includes a series connection of first and second resistors each of which resistors forms a portion of said resistance means; said thyristors are grouped into first and second groups; said monitoring circuit generates first and second signals indicative of the states of the thyristors in said first and second groups, respectively; said control switch means includes an evaluation circuit responsive to said first and second signals, said evaluation circuit causing the short-circuiting of said first resistor when said first-signal or said second signal indicates the failure of a thyristor of its respective group, and said evaluation circuit causing the short-circuiting of said series connection of said first and second resistors when said first and second signals indicate a failure of a thyristor of their respective groups.

Claim 5

A circuit arrangement in accordance with claim 3 in which said evaluation circuit comprises a NOR gate and a NAND gate each of which is fed the output signals from said monitoring circuit.

Claim 6

A circuit arrangement in accordance with claim 4 in which said monitoring circuit includes: a first group of fuses each connected in series with one of the thyristors of said first group; a second group of fuses each connected in series with one of the thyristors of said second group; a first circuit comprising a first group of series connected alarm contacts each being associated with one of the fuses of said first group of fuses, said first circuit having one end adapted to be connected to a d-c voltage source; a second circuit comprising a second group of series connected alarm contacts each being associated with one of the fuses of said second group of fuses, said second circuit having one end adapted to be connected to said source; first and second inverters having inputs connected to the other ends of said first and second circuits, respectively, and outputs connected to said evaluation circuit.