Timing mode selector

Claim 1

Timing mode selector comprising in combination a clock pulse generator for supplying a continuous series of timing pulses, a first pair of integrated-circuit counters, said counters being connected in series to the output of said generator for providing a predetermined first mode pulse rate output, a second pair of integrated-circuit counters, said second counters being connected in series to said first mode output for providing a predetermined second mode pulse rate output, a unitary integrated circuit for alternatively selecting said first or second mode output comprising four NAND gates, each of said NAND gates having two input circuits and an output, means for connecting a mode-control signal to said unitary integrated circuit, said mode-control signal having an on-state for one of said modes and an off-state for the other of said modes, an output circuit from said unitary integrated circuit for transmitting the selected one of said modes, first circuit means for connecting said first and second mode pulse rate outputs to the inputs of two of said NAND gates, second circuit means for connecting said mode-control signal connecting means to two other inputs of said NAND gates, and third circuit means for connecting said output circuit to one of said NAND gate outputs.