Circuit arrangement for a selective signal receiver, particularly for use in telephone systems

Claim 1

A circuit arrangement for a selective signal receiver which, for frequency recognition, counts the zero crossings of an input signal occurring at each signal-frequency half cycle and measures the time distances between the zero crossings, particularly for use in telephone systems, comprising a circuit operable between a normal "off" state and an "on" state, a zero-crossing counter coupled to said circuit, said circuit responding to the occurrence of a zero crossing to change to the "on" state and provide a counting pulse for the zero-crossing counter, said circuit remaining in said "on" state for a dwell time which is only little shorter than the duration of the signal-frequency half cycle and remaining uninfluenced by additional zero crossings occurring during said dwell time, said circuit which measures the time distance between the zero crossings including means for counting clock pulses during said dwell time and means for providing an output at the end of said dwell time if the number of clock pulses counted is within a prescribed range.