Circuit for driving a DC motor for a clock

Claim 2

A control circuit for a clock having a time indicating mechanism, which control circuit regulates the intermittent driving of a DC motor by a predetermined amount at predetermined time intervals so as to actuate said time indicating mechanism, said control circuit having a timing pulse generating circuit for generating timing pulses at said predetermined time intervals so as to actuate said control circuit and means for providing an energizing voltage for driving said motor, wherein the improvement comprises a holding circuit coupled at its input to said timing pulse generating circuit and at its output to said motor, said holding circuit being actuated to be self-held each time a timing pulse is applied thereto thereby enabling said motor to be driven by said energizing voltage, and switching means, coupled to said time indicating mechanism, so as to be actuated each time said motor is driven by said predetermined amount, said switching means being coupled to the input of said holding circuit so as to release the self-holding thereof when the switching means is actuated, whereby said motor is deenergized exactly at the completion of the driving thereof by said predetermined amount without being affected by the variation in the amplitude of said energizing voltage and the variation in the load on said motor.

Claim 3

A control circuit according to claim 1, wherein said timing pulse generating circuit generates low level timing pulses, said means for providing an energizing voltage includes a first conductor to which a plus potential is applied and a second conductor to which a minus potential is applied, and said holding circuit comprises a PNP-type transistor having is base coupled to said timing pulse generating circuit and its emitter coupled to the first conductor, an NPN-type transistor having its base coupled to the collector of said PNP-type transistor and its emitter coupled to the second conductor while the collector thereof is coupled to the first conductor, and a feed back resistor coupled between the collector of said NPN-type transistor and the base of said PNP-type transistor, the collector of said NPN-type transistor being coupled to said motor.

Claim 4

A control circuit according to claim 2, further comprising an additional PNP-type transistor having its emitter coupled to the first conductor and its collector coupled to one end of said motor, the other end of which is coupled to the second conductor, the base of said additional PNP-type transistor being coupled to the collector of said NPN-type transistor.

Claim 5

A control circuit according to claim 1, wherein said timing pulse generating circuit generates low level timing pulses, and said switching means comprises an ON-OFF switch coupled at its one terminal to the first conductor, a capacitor coupled at its one end to the other terminal of said ON-OFF switch and at its other end to the base of said first-mentioned PNP-type transistor, and a discharge resistor connected in parallel with said capacitor.

Claim 6

A control circuit for a clock having a time indicating mechanism, which control circuit regulates the intermittent driving of a DC motor by a predetermined amount at predetermined time intervals so as to actuate said time indicating mechanism, said control circuit having a timing pulse generating circuit for generating low level timing pulses at said predetermined time intervals so as to actuate said control circuit, and means, including first and second conductors, for providing a DC energizing voltage for driving said motor, with the potential on said first conductor being positive with respect to the potential on said second conductor, wherein the improvement comprises a first PNP-type transistor having its base coupled to the output of said timing pulse generating circuit and its emitter coupled to said first conductor, an NPN-type transistor having its base coupled to the collector of said first PNP-type transistor and its emitter coupled to the second conductor while the collector thereof is coupled to the first conductor, a feed back resistor coupled between the collector of said NPN-type transistor and the base of said first PNP-type transistor, a second PNP-type transistor having its base coupled to the collector of said NPN-type transistor and its emitter coupled to the first conductor while the collector thereof is coupled to one terminal of said motor, the other terminal of which is coupled to the second conductor, an ON-OFF switch having one terminal coupled to the first conductor, said ON-OFF switch being coupled to said time indicating mechanism so as to be closed each time said motor is driven by said predetermined amount, a capacitor coupled at its one end to the other terminal of said ON-OFF switch and at its other end to the base of said first PNP-type transistor, and a discharge resistor connected in parallel with said capacitor, so that said motor is driven each time a timing pulse is applied to said first PNP-type transistor and deenergized each time said motor is driven by said predetermined amount, without being affected by the variation in the amplitude of said energizing voltage and the variation in the load on said motor.

Claim 7

A control circuit for a clock having a time indicating mechanism, which control circuit regulates the intermittent driving of a DC motor by a predetermined amount at predetermined time intervals so as to actuate said time indicating mechanism, said control circuit having a timing pulse generating circuit for generating low level timing pulses at said predetermined time intervals so as to actuate said control circuit, and means, including first and second conductors, for providing a DC energizing voltage for driving said motor, with the potential on said first conductor being positive with respect to the potential on said second conductor, wherein the improvement comprises a first PNP-type transistor having its base coupled to the output of said timing pulse generating circuit and its emitter coupled to said first conductor, an NPN-type transistor having its base coupled to the collector of said first PNP-type transistor and its emitter coupled to the second conductor while the collector thereof is coupled to the first conductor, a feed back resistor coupled between the collector of said NPN-type transistor and the base of said first PNP-type transistor, a second PNP-type transistor having its base coupled to the collector of said NPN-type transistor and its emitter coupled to the first conductor while the collector thereof is coupled to one terminal of said motor, the other terminal of which is coupled to the second conductor, an ON-OFF switch having one terminal coupled to the first conductor, said ON-OFF switch being coupled to said time indicating mechanism so as to be closed each time said motor is driven by said predetermined amount, a capacitor coupled at its one end to the other terminal of said ON-OFF switch and at its other end to the base of said first PNP-type transistor, and a discharge resistor connected in parallel with said capacitor, so that said motor is driven each time a timing pulse is applied to said first PNP-type transistor and deenergized each time said motor is driven by said predetermined amount, without being affected by the variation in the amplitude of said energizing voltage and the variation in the load on said motor.