Recirculating type analog to digital converter

Claim 2

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first and second signal, the first signal being an inverse of a signal appearing at the time delay input and the second signal being a selected function of the time delay input signal corresponding to a desired conversion of an applied analog signal; switch means for coupling the time delay input to receive the applied analog signal and for repetitively coupling the time delay input to receive the first and second signals; means for coupling the time delay output to the algorithmic means input; and comparator means coupled to the time delay for producing a digital output signal.

Claim 3

An analog to digital converter as in claim 1 wherein means for coupling comprises a capacitor.

Claim 4

An analog to digital converter as in claim 2 wherein algorithmic means comprises a transformer having: a primary winding coupled to receive an input; an auxiliary secondary winding for producing the first signal; and a center tapped secondary winding having positive and negative ends for producing the second signal and a center tap for receiving a reference voltage.

Claim 5

An analog to digital converter as in claim 3 wherein the auxiliary secondary winding has a transformation ratio of -1.

Claim 6

An analog to digital converter as in claim 3 wherein the center tapped secondary winding has a transformation ratio of 4.

Claim 7

An analog to digital converter as in claim 1 wherein algorithmic means comprise: coupling means for coupling to a reference voltage source; a first resistor coupled to the coupling means and the means for coupling the time delay output to the algorithmic means input; a second resistor coupled to the coupling means and the time delay output; a third resistor coupled to the means for coupling the time delay output to the algorithmic means input and ground and having a tap for producing the first signal; and means for coupling to the first resistor and to the second resistor for producing the second signal.

Claim 8

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first and second signal, the first signal being an inverse of a signal appearing at the time delay input and the second signal being a selected function of the time delay input signal corresponding to a desired conversion of an applied analog signal; switch means for coupling the time delay input to receive the applied analog signal and for repetitively coupling the time delay input to receive the first and second signals in a selected sequence; means for coupling the time delay output to the algorithmic means input; and comparator means coupled to the time delay for producing a digital output signal.

Claim 9

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first and second signal, the first signal being an inverse of a signal appearing at the time delay input and the second signal being a selected function of the time delay input signal corresponding to a desired conversion of an applied analog signal; switch means for coupling the time delay input to receive the applied analog signal and for repetitively coupling the time delay input to receive the first and second signals in a selected sequence; means for coupling the time delay output to the algorithmic means input; and comparator means coupled to the time delay for producing a digital output signal.

Claim 10

An analog to digital converter as in claim 7 wherein comparator means comprise: a comparator having a first input coupled to the time delay, a reference input and an output; and means coupled to the comparator reference input for adjusting the potential of the reference input.

Claim 11

An analog to digital converter as in claim 8 wherein means for adjusting the potential at the reference input comprise: a digital storage; a digital multiplexer coupled to receive the comparator output and to the digital storage for applying the comparator output to the digital storage in response to the analog switch coupling the time delay to receive the ground potential; and voltage adjusting means connected to the comparator reference input and to the digital storage for adjusting the potential at the reference input.

Claim 12

An analog to digital converter as in claim 9 wherein voltage adjusting means comprise: a capacitor connected to the reference input; current means coupled to the capacitor and to the digital storage for adjusting the voltage across the capacitor.

Claim 13

An analog to digital converter as in claim 7 wherein algorithmic means comprises a transformer having; a primary winding coupled to receive an input; an auxiliary secondary winding for producing the second signal; and a center tapped secondary winding having positive and negative ends for producing the first signal and a center tap for receiving a reference voltage.

Claim 14

An analog to digital converter as in claim 11 wherein the auxiliary secondary winding has a transformation ratio of -1.

Claim 15

An analog to digital converter as in claim 11 wherein the center tapped secondary has a transformation ratio of 4.

Claim 16

An analog to digital converter as in claim 7 wherein means for coupling comprise an amplifier; and a first capacitor, a second capacitor, and a third capacitor, each capacitor having one terminal commonly coupled to the amplifier.

Claim 17

An analog to digital converter as in claim 14 wherein algorithmic means comprise: first means for coupling to a negative reference voltage; second means for coupling to a positive reference voltage; a first resistor coupled between the first capacitor and the first means; a second resistor coupled between the second capacitor and the second means; a third resistor coupled between the third capacitor and ground and having a tap for producing the first signal; and means for coupling to the connection between the first capacitor and the first resistor and to the connection between the second capacitor and second resistor for producing the second signal.

Claim 18

An analog to digital converter as in claim 8 wherein the selected sequence comprises: the analog switch first coupling an applied analog signal to the time delay input; next repetitively coupling the time delay input a plurality of times to receive the first and second signals in a sequence and then coupling the ground potential to the time delay input.

Claim 19

An analog to digital converter as in claim 8 wherein the selected sequence comprises: the analog switch first coupling the time delay input to the ground potential and then repetitively coupling the time delay input a plurality of times to receive the first and second signals in a sequence.

Claim 20

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first and second signal, the first signal being an inverse of a signal appearing at the time delay input and the second signal being a selected function of the time delay input signal corresponding to a desired conversion of an applied analog signal; clock means for producing a first clock signal and a second clock signal, the second clock signal having a repetition rate which is a multiple of the repetition rate of the first clock signal; switch means for coupling the time delay input to receive an applied analog signal and for repetitively coupling the time delay input to receive the first and second signals in response to the first clock signal; means for coupling the time delay output to the algorithmic means input; a comparator responsive to the second clock signal and having an input coupled to the time delay for producing a digital output signal.

Claim 21

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first and second signal, the first signal being an inverse of a signal appearing at the time delay input and the second signal being a selected function of the time delay input signal corresponding to a desired conversion of an applied analog signal; clock means for producing a first clock signal and a second clock signal, the second clock signal having a repetition rate which is a multiple of the repetition rate of the first clock signal; switch means for coupling the time delay input to receive an applied analog signal and for repetitively coupling the time delay input to receive the first and second signals in response to the first clock signal; means for coupling the time delay output to the algorithmic means input; a comparator responsive to the second clock signal and having an input coupled to the time delay for producing a digital output signal.

Claim 22

An analog to digital converter as in claim 18 wherein the second clock signal has a repetition rate twice that of the first clock signal.

Claim 23

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first, second and third signal, the first signal being an inverse of a signal appearing at the time delay input, the second signal being a selected function corresponding to a desired conversion of an applied analog signal; a time delay; switch means for coupling the time delay to receive an applied analog signal and to receive a ground potential in a first selected sequence and for repetitively coupling the time delay input to receive the first, second, and third signals in a second selected sequence; means for coupling the time delay to the algorithmic means; a comparator coupled to the time delay for producing a digital output signal havng logic levels; a gain control having variable gain; means for serially coupling in a loop that analog switch, the time delay, the gain control, the means for coupling and the algorithmic means; and means coupled to the gain control for varying the gain of the gain control in response to variations of the third signal.

Claim 24

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first, second and third signal, the first signal being an inverse of a signal appearing at the time delay input, the second signal being a selected function corresponding to a desired conversion of an applied analog signal; a time delay; switch means for coupling the time delay to receive an applied analog signal and to receive a ground potential in a first selected sequence and for repetitively coupling the time delay input to receive the first, second, and third signals in a second selected sequence; means for coupling the time delay to the algorithmic means; a comparator coupled to the time delay for producing a digital output signal havng logic levels; a gain control having variable gain; means for serially coupling in a loop that analog switch, the time delay, the gain control, the means for coupling and the algorithmic means; and means coupled to the gain control for varying the gain of the gain control in response to variations of the third signal.

Claim 25

An analog to digital converter as in claim 20 wherein means for varying the gain comprise: a digital storage for storing the logic levels; a digital multiplexer coupled to receive the digital output signal for applying the digital output signal to the digital storage in response to the switch means coupling the third signal potential to the time delay; and means coupled to the digital storage for varying the gain of the gain control in response to the logic levels stored in the digital storage.

Claim 26

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first signal, a second signal and a third signal, the first signal being an inverse of a signal appearing at the time delay input, the second and third signals being second and third selected functions respectively of the time delay input signal corresponding to a desired conversion of an applied analog signal; switch means for coupling the time delay input to receive the applied analog signal and for coupling in a selected sequence the time delay input to receive the first, second and third signals; means for coupling the time delay output to the algorithmic means input; and comparator means coupled to the time delay for producing a digital output signal.

Claim 27

An analog to digital converter comprising: a time delay having an input and an output; algorithmic means having an input for generating a first signal, a second signal and a third signal, the first signal being an inverse of a signal appearing at the time delay input, the second and third signals being second and third selected functions respectively of the time delay input signal corresponding to a desired conversion of an applied analog signal; switch means for coupling the time delay input to receive the applied analog signal and for coupling in a selected sequence the time delay input to receive the first, second and third signals; means for coupling the time delay output to the algorithmic means input; and comparator means coupled to the time delay for producing a digital output signal.

Claim 28

An analog to digital converter as in claim 22 wherein means for coupling comprise a capacitor.

Claim 29

An analog to digital converter as in claim 23 wherein algorithmic means comprise a transformer having: a primary winding coupled to receive an input; a first secondary winding for producing the first signal; a second secondary winding for producing the second signal; and a third secondary winding for producing the third signal.

Claim 30

An analog to digital converter as in claim 24 wherein the second scondary winding is center tapped for receiving a first reference voltage.

Claim 31

An analog to digital converter as in claim 24 comprising means coupled to the third secondary winding for applying a second signal thereto.

Claim 32

An analog to digital converter as in claim 26 wherein the desired conversion is a digital code representing the value ##EQU1## V xi being the voltage of the second signal when the switch means couples the time delay input to receive the third signal, -A being the transformaton ratio of the third secondary winding to the primary winding, V 0 being the sampled voltage of an applied analog signal to be converted and m being the number of times the switch means couples the time delay input to receive the third signal.