US3970874A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuitry for controlling shutter time in accordance with a manually adjustable resistor
Assignee: Pentax Corp
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Filing: 1974-09-06
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Granted: 1976-07-20
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Expires: 1994-09-06
Abstract
Abstract An output stage transistor of a control circuit provides a manually adjustable amount of charging current to a timing capacitor. The control circuit is arranged so that the charging current changes by a factor of two for each resistance change by a factor of the square root of two in a manually variable resistor.
Inventors
- 👤 Masahiro Kawasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:57
CPC Classifications
G; G03; G03B; G03B7/00; G03B7/08; G03B7/081; G03B7/083
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
369 words
In a camera arrangement having a d.c. power source, an electromagnet, a timing capacitor, a timing switch for switchably enabling charging current to flow through the timing capacitor to develop a voltage across the timing capacitor, and switching circuit means connected to respond to the voltage across the timing capacitor to switchably energize the electromagnet, the combination comprising: a constant current source; first and second transistors each having a base electrode, an emitter electrode, and collector electrode; the first transistor having a base-emitter junction between its base and emitter electrode, and having its collector electrode coupled to the constant current source; the second transistor having a base-emitter junction between its base and emitter electrodes, and having its collector electrode connected to one end of the timing capacitor; the other end of the timing capacitor being connected to one terminal of the d.c. power source, and the other terminal of the d.c. power source being connected to the emitter electrode of the second transistor so that there is defined a circuit loop through which the charging current flows in an amount which depends upon the magnitude of voltage defined across the base-emitter junction of the second transistor; first and second resistors; the first transistor having its base and emitter electrodes connected to opposite ends of the first resistor so that the first resistor is in parallel-circuit relationship with the base-emitter junction of the first transistor; the second transistor having its base and emitter electrodes connected to opposite ends of the second resistor so that the second resistor is in parallel-circuit relationship with the base-emitter junction of the second transistor; first and second current amplification circuit means having substantially the same current gain, the first current amplification circuit means being connected between the constant current source and the first resistor so as to serve as a feedback circuit for the first transistor, the second current amplification circuit means being connected between the constant current source and the second transistor; and one of said first and second resistors being manually adjustable to control the magnitude of the voltage defined across the base-emitter junction of the second transistor so as thereby to control the amount of charging current flowing through the timing capacitor.
Claim 2
Dependent Claim
369 words
In a camera arrangement having a d.c. power source, an electromagnet, a timing capacitor, a timing switch for switchably enabling charging current to flow through the timing capacitor to develop a voltage across the timing capacitor, and switching circuit means connected to respond to the voltage across the timing capacitor to switchably energize the electromagnet, the combination comprising: a constant current source; first and second transistors each having a base electrode, an emitter electrode, and collector electrode; the first transistor having a base-emitter junction between its base and emitter electrode, and having its collector electrode coupled to the constant current source; the second transistor having a base-emitter junction between its base and emitter electrodes, and having its collector electrode connected to one end of the timing capacitor; the other end of the timing capacitor being connected to one terminal of the d.c. power source, and the other terminal of the d.c. power source being connected to the emitter electrode of the second transistor so that there is defined a circuit loop through which the charging current flows in an amount which depends upon the magnitude of voltage defined across the base-emitter junction of the second transistor; first and second resistors; the first transistor having its base and emitter electrodes connected to opposite ends of the first resistor so that the first resistor is in parallel-circuit relationship with the base-emitter junction of the first transistor; the second transistor having its base and emitter electrodes connected to opposite ends of the second resistor so that the second resistor is in parallel-circuit relationship with the base-emitter junction of the second transistor; first and second current amplification circuit means having substantially the same current gain, the first current amplification circuit means being connected between the constant current source and the first resistor so as to serve as a feedback circuit for the first transistor, the second current amplification circuit means being connected between the constant current source and the second transistor; and one of said first and second resistors being manually adjustable to control the magnitude of the voltage defined across the base-emitter junction of the second transistor so as thereby to control the amount of charging current flowing through the timing capacitor.
Claim 3
Dependent Claim
21 words
The combination of claim 1 wherein the first and second current amplification circuit means each comprise a transistor and a diode.
Claim 4
Dependent Claim
20 words
The combination of claim 1 wherein the constant current source comprises a field effect transistor connected in a self-bias circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-20 | 1980-01-19 | 1980-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-20 | 1984-01-19 | 1984-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-20 | 1988-01-19 | 1988-07-20 | $7700.00 | Window Closed / Lapsed |