US3970867A
Expired / Lapsed
US
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Synchronous counter/divider using only four NAND or NOR gates per bit
Assignee: Texas Instruments Inc
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Filing: 1975-02-18
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Granted: 1976-07-20
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Expires: 1995-02-18
Abstract
Abstract A plural bit-stage synchronous counter/divider wherein each bit-stage comprises four multiple-input inverting gates in flip-flop configuration with the output of the first and second gates connected to one of the multiple inputs of the third and fourth gates respectively, one of the inputs of each of said first and second gates connected to a clock pulse line, the outputs of said third and fourth gates connected to a second input of said multiple inputs of each of said second and fourth gates and of said first and third gates respectively and third inputs of said multiple inputs of said third and fourth gates connected to clear and preset lines respectively and a clock pulse generator means providing clock pulses of a length between one and two times the propagation delay period of the slowest of said gates.
Inventors
- 👤 Horst Leuschner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:48
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/64; H03K23/66; H03K23/665; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
249 words
A synchronous counter/divider circuit comprising: a. a plurality of serially connected flip-flop stages with each stage receiving outputs from each of the preceding stages; b. a clock pulse generator; c. each of said flip-flop stages comprising a pair of multiple input inverting steering gates and a pair of multiple input inverting latch gates, each of said steering gates having a clock pulse input common to said steering gate pair, individual inputs from each preceding stage common to said steering gate pair and a feedback input, each of said pair of latch gates having a feedback input, an input from a corresponding steering gate output of said stage, one additional input and an output connected in common to said feedback inputs of the opposite latch gate and opposite steering gate of said stage, the output of one of said latch gates of each stage being the output of said stage; d. said clock pulse generator comprising means to produce a clock pulse having a duration of between one and two times the propagation delay time of the slowest of said inverting gates in response to an input clock signal, said clock pulse being applied to said clock pulse inputs of each of said stages; and e. said additional inputs of one of said latch gates in each of said stages being connected together as a preset input and said additional inputs of the other of said latch gates of each of said stages being connected together as a clear input.
Claim 2
Dependent Claim
249 words
A synchronous counter/divider circuit comprising: a. a plurality of serially connected flip-flop stages with each stage receiving outputs from each of the preceding stages; b. a clock pulse generator; c. each of said flip-flop stages comprising a pair of multiple input inverting steering gates and a pair of multiple input inverting latch gates, each of said steering gates having a clock pulse input common to said steering gate pair, individual inputs from each preceding stage common to said steering gate pair and a feedback input, each of said pair of latch gates having a feedback input, an input from a corresponding steering gate output of said stage, one additional input and an output connected in common to said feedback inputs of the opposite latch gate and opposite steering gate of said stage, the output of one of said latch gates of each stage being the output of said stage; d. said clock pulse generator comprising means to produce a clock pulse having a duration of between one and two times the propagation delay time of the slowest of said inverting gates in response to an input clock signal, said clock pulse being applied to said clock pulse inputs of each of said stages; and e. said additional inputs of one of said latch gates in each of said stages being connected together as a preset input and said additional inputs of the other of said latch gates of each of said stages being connected together as a clear input.
Claim 3
Dependent Claim
55 words
A synchronous counter/divider circuit as defined in claim 1 wherein said clock pulse generator comprises an inverter and a NOR gate, the input of said inverter and one input of said NOR gate being connected to receive a clock signal, and another input of said NOR gate being connected to the output of said inverter.
Claim 4
Dependent Claim
15 words
A synchronous counter/divider circuit as defined in claim 1 wherein said gates are NAND gates.
Claim 5
Dependent Claim
15 words
A synchronous counter/divider circuit as defined in claim 1 wherein said gates are NOR gates.
Claim 6
Dependent Claim
15 words
A synchronous counter/divider circuit as defined in claim 2 wherein said gates are NAND gates.
Claim 7
Dependent Claim
15 words
A synchronous counter/divider circuit as defined in claim 2 wherein said gates are NOR gates.
Claim 8
Dependent Claim
40 words
A synchronous counter/divider circuit as defined in claim 2 wherein said clock pulse generator comprises in addition a Schmitt trigger circuit between the clock signal input and said input to said inverter and said one input of said NOR gate.
Claim 9
Dependent Claim
40 words
A synchronous counter/divider circuit as defined in claim 5 wherein said clock pulse generator comprises in addition a Schmitt trigger circuit between the clock signal input and said input to said inverter and said one input of said NOR gate.
Claim 10
Dependent Claim
40 words
A synchronous counter/divider circuit as defined in claim 6 wherein said clock pulse generator comprises in addition a Schmitt trigger circuit between the clock signal input and said input to said inverter and said one input of said NOR gate.
References Cited (Backward Citations)
US3535544A
Cited
US3467839A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-20 | 1980-01-19 | 1980-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-20 | 1984-01-19 | 1984-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-20 | 1988-01-19 | 1988-07-20 | $7700.00 | Window Closed / Lapsed |