US3969717A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital circuit to eliminate display flicker
Assignee: Hitachi Ltd
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Filing: 1974-11-20
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Granted: 1976-07-13
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Expires: 1994-11-20
Abstract
Abstract A digital circuit has a memory circuit and a logical circuit connected in cascade between first and second delay circuits. The first delay circuit controls an input signal to the digital circuit, so that the delay of the input signal due to a stage or stages preceding to the digital circuit may fall within a delay by the first delay circuit, and the second delay circuit controls an output signal from the digital circuit, so that delays due to the memory and logical circuits may fall within a delay by the second delay circuit, whereby the output signal is made apparently free from the delays due to the preceding stage or stages and to the memory and logical circuits.
Inventors
- 👤 Yoshikazu Hatsukano
- 👤 Kosei Nomiya
- 👤 Hiroto Kawagoe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; G; G09; G09G; G09G3/00; G09G3/04; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
195 words
A circuit comprising: a plurality of input terminals to which respective information signals are applied; a logical circuit, coupled to receive said information signals and to effect a prescribed logical operation thereon; an output circuit, coupled to said logical circuit, for providing an indication of the operation of said logical circuit on said information signals, including a display device for luminously displaying the result of the operation of said logical circuit on said information signals; a plurality of first delay means, respectively connected between said plurality of input terminals and said logical circuit, for controlling the application of said information signals to said logical circuit in accordance with a first pulse signal; a multiplicity of second delay means, respectively connected between said logical circuit and said output circuit, for receiving the result of the operation of said logical circuit and applying said result to said output circuit in accordance with a second pulse signal having a phase difference relative to said first pulse signal; and an input shift register for supplying information signals at the outputs of respective stages thereof and for shifting the contents thereof in synchronism with said first and second pulse signals.
Claim 2
Dependent Claim
195 words
A circuit comprising: a plurality of input terminals to which respective information signals are applied; a logical circuit, coupled to receive said information signals and to effect a prescribed logical operation thereon; an output circuit, coupled to said logical circuit, for providing an indication of the operation of said logical circuit on said information signals, including a display device for luminously displaying the result of the operation of said logical circuit on said information signals; a plurality of first delay means, respectively connected between said plurality of input terminals and said logical circuit, for controlling the application of said information signals to said logical circuit in accordance with a first pulse signal; a multiplicity of second delay means, respectively connected between said logical circuit and said output circuit, for receiving the result of the operation of said logical circuit and applying said result to said output circuit in accordance with a second pulse signal having a phase difference relative to said first pulse signal; and an input shift register for supplying information signals at the outputs of respective stages thereof and for shifting the contents thereof in synchronism with said first and second pulse signals.
Claim 3
Dependent Claim
42 words
A display circuit according to claim 1, wherein said logical circuit comprises a first MOSFET matrix for decoding said information signals into decimal signals and a second MOSFET matrix connected to said first matrix for decoding said decimal signals into display signals.
Claim 4
Dependent Claim
18 words
A display circuit according to claim 2, wherein each of said first delay means comprises a flip-flop circuit.
Claim 5
Dependent Claim
18 words
A display circuit according to claim 3, wherein each of said second delay means comprises a flip-flop circuit.
References Cited (Backward Citations)
US3179883A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-13 | 1980-01-12 | 1980-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-13 | 1984-01-12 | 1984-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-13 | 1988-01-12 | 1988-07-13 | $7700.00 | Window Closed / Lapsed |