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US3968491A Expired / Lapsed US ⏱️ 0.0 years remaining

Radar rangemeter

Assignee: United States Department of the Navy
•
Filing: 1974-11-25
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Granted: 1976-07-06
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Expires: 1994-11-25
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Abstract

Abstract A range-determining circuit which counts the time from the transmission of detection-signal to its echo return, in units corresponding directly to the distance that the detection signal travels.

Inventors

  • 👤 Jeffrey L. Silberberg

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 13:02
CPC Classifications
H; H10; H10P; H10P34/00; H10P34/40; H10P34/42

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 242 words
A range determining and display circuit for use with reflected energy ranging systems producing a first signal upon the occurence of transmission of a detection signal and a second signal upon the return target reflection comprising: first conditioning means for receiving said first signal; second conditioning means for receiving said second signal; digital clock means for generating timing signals spaced apart in time at intervals corresponding to the propagation time necessary for said detection signal to travel twice the distance of the lowest discrete range distance to be displayed, said timing signals being coupled to said first conditioning means as an input; digital counting means for counting said timing signals, having a first input terminal connected to the output of said first conditioning means, a second input terminal connected to the output of said second conditioning means, and a clock input terminal connected to the output of said digital clock means; buffer means connected to the output of said clock means for storing a selected output signal from said counting means; and digital display means connected to the output of said buffer means for displaying in numerical format the corresponding decimal value of said stored selected counting means output signal stored in said buffer means; whereby said first signal enables said counting means to begin counting said timing signals, and said second signal dis-enables said counting means thereby causing the range of said target to be displayed directly in digital numerical format.
Claim 2
Dependent Claim 242 words
A range determining and display circuit for use with reflected energy ranging systems producing a first signal upon the occurence of transmission of a detection signal and a second signal upon the return target reflection comprising: first conditioning means for receiving said first signal; second conditioning means for receiving said second signal; digital clock means for generating timing signals spaced apart in time at intervals corresponding to the propagation time necessary for said detection signal to travel twice the distance of the lowest discrete range distance to be displayed, said timing signals being coupled to said first conditioning means as an input; digital counting means for counting said timing signals, having a first input terminal connected to the output of said first conditioning means, a second input terminal connected to the output of said second conditioning means, and a clock input terminal connected to the output of said digital clock means; buffer means connected to the output of said clock means for storing a selected output signal from said counting means; and digital display means connected to the output of said buffer means for displaying in numerical format the corresponding decimal value of said stored selected counting means output signal stored in said buffer means; whereby said first signal enables said counting means to begin counting said timing signals, and said second signal dis-enables said counting means thereby causing the range of said target to be displayed directly in digital numerical format.
Claim 3
Dependent Claim 65 words
The range determining and display circuit of claim 1 wherein said buffer means includes division means connected to the output of said second signal conditioning means, said division means for generating a load enable signal upon the occurence of a predetermined number of said second signals whereby said buffer means stores the output signal of said digital counter means upon receiving said load enable signal.
Claim 4
Dependent Claim 22 words
The range determining and display circuit of claim 1 wherein said digital clock means operates at a frequency of 809.38 k Hz.

References Cited (Backward Citations)

US2941151A Cited
US3117317A Cited
US3199104A Cited
US3545861A Cited
US3539978A Cited
US3555549A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-07-06 1980-01-05 1980-07-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-07-06 1984-01-05 1984-07-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-07-06 1988-01-05 1988-07-06 $7700.00 Window Closed / Lapsed

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