US3967206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual edge and level (DEL) flip-flop
Assignee: United States Department of the Army
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Filing: 1975-03-19
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Granted: 1976-06-29
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Expires: 1995-03-19
Abstract
Abstract The dual edge and level (DEL) flip-flop not only is sensitive to both positive and negative edges and level inputs, but the device can be made sensitive to (1) positive edges only, (2) negative edges only, (3) both positive and negative edges, or (4) neither positive or negative edges. In any case, the output can be controlled by the level inputs which override the edge operation.
Inventors
- 👤 Donald L. Roberson
- 👤 Donald K. Fronek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:31
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
151 words
A dual edge flip-flop means having first through fourth input terminals and first and second flip-flop output terminals; first signal means having waveforms which have both positive and negative edges being connected to supply said first input terminal; second and third signals being connected to said second and third input terminals so as to determine that the flip-flop means is sensitive to positive edges, negative edges, or both positive and negative edges of said first signal or is insensitive to said first signal; and a binary signal being fed to said fourth input terminal such that the outputs on the first and second flip-flop output terminals will assume one binary state when the binary signal is a "0" and the opposite state when the binary signal is a "1" when said first signal is fed into said first input terminal to which said second and third signals make the flip-flop sensitive.
Claim 2
Dependent Claim
151 words
A dual edge flip-flop means having first through fourth input terminals and first and second flip-flop output terminals; first signal means having waveforms which have both positive and negative edges being connected to supply said first input terminal; second and third signals being connected to said second and third input terminals so as to determine that the flip-flop means is sensitive to positive edges, negative edges, or both positive and negative edges of said first signal or is insensitive to said first signal; and a binary signal being fed to said fourth input terminal such that the outputs on the first and second flip-flop output terminals will assume one binary state when the binary signal is a "0" and the opposite state when the binary signal is a "1" when said first signal is fed into said first input terminal to which said second and third signals make the flip-flop sensitive.
Claim 3
Dependent Claim
75 words
A flip-flop as set forth in claim 1 further comprising fifth and sixth level input terminals connected to said dual edge flip-flop means so as to make the flip-flop means a dual edge and level flip-flop; and said fifth and sixth inputs overriding the edge operations when either of the inputs are of a predetermined first binary value and not affecting the operation when both fifth and sixth inputs are of the other binary value.
Claim 4
Dependent Claim
57 words
A flip-flop as set forth in claim 2 wherein the state of the outputs at first and second output terminals is one value when only said fifth level input terminal is receiving a "0" level and said state reversing at said first and second output terminals when only said sixth level input terminal is receiving a "0".
Claim 5
Dependent Claim
75 words
A flip-flop as set forth in claim 3 having circuit means comprising first and second single edge and level flip-flops each having four input terminals and two output terminals; and gating circuitry connected between the input signals and the terminals of said first and second single edge and level flip-flops such that the outputs of one of said single edge and level flip-flops correspond with the output terminals of said dual edge and level flip-flop.
References Cited (Backward Citations)
US3446994A
Cited
US3541356A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-29 | 1979-12-29 | 1980-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-29 | 1983-12-29 | 1984-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-29 | 1987-12-29 | 1988-06-29 | $7700.00 | Window Closed / Lapsed |