Digital FFT processor using random access memory

Claim 1

In a system for the digital implementation of a fast Fourier transform (FFT), the combination of: a plurality of elements for performing FFT operations with each element including, first and secnd random access memories (RAMs) for storing signals, with said second memory connected to said first memory forming a delay line; a third memory for storing the rotation vector of said FFT; a multiplier having as inputs the outputs of said second memory and said third memory and providing at its output the product of said signal and said rotation vector; sum and difference circuits having as inputs the output of said first memory and said multiplier and providing at its output the sum and difference signals required for said element by the FFT algorithm; an address counter connected to said first, second, and third memories for accessing said memories; and a clock connected to said memories and to said address counter for controlling timing operations of said memories and of said address counter.

Claim 13

A method for the digital implementation of a fast Fourier transform (FFT), including th steps of: storing signals in first and second random access memories (RAMS); storing the rotation vector of said FFT in a third memory; multiplying the contents of said second and third memories in a multiplier; simultaneously adding and subtracting the contents of said first memory and the output of said multiplier to obtain S sum , S diff as required by the FFT algorithm; accessing said memories with an address counter; timing the operation of said memories with a clock; and connecting a plurality of like units as described above for the computation of said FFT.

Claim 14

A method for the digital implementation of a fast Fourier transform (FFT), including th steps of: storing signals in first and second random access memories (RAMS); storing the rotation vector of said FFT in a third memory; multiplying the contents of said second and third memories in a multiplier; simultaneously adding and subtracting the contents of said first memory and the output of said multiplier to obtain S sum , S diff as required by the FFT algorithm; accessing said memories with an address counter; timing the operation of said memories with a clock; and connecting a plurality of like units as described above for the computation of said FFT.