Abstract A vibration gravitometer having leaf spring vanes located in respective cells in a thermally conductive block. Each cell contains a different gas at ambient atmospheric temperature and pressure. One cell contains air, the other a gas, the gravity of which is to be monitored, "gravity" being defined as the ratio of the density of the gas to the density of air at the same temperature and pressure. The gravity of one specific gas of constant composition is a constant. The vanes are vibrated at the same or different frequencies dependent upon the air and gas densities. These frequencies are multiplied and combined in a digital calculator that utilizes a frequency-time reciprocal to divide. A readout circuit multiplies the output of the calculator by a constant of proportionality and indicates the gravity.
A rate divider comprising: a storage register having a plurality of stages; a counter having a plurality of stages and having count and reset inputs; a coincidence gate having an output and having plural inputs connected from the stages of both said storage register and said counter for producing an output pulse at said output thereof when the number stored in said counter becomes equal to the number stored in said storage register; clock means having an output signal frequency and an output connected to said counter count input, said coincidence gate having an output signal of a frequency equal to the clock means frequency divided by the number stored in said register, said coincidence gate also being connected to the reset input of said counter; and means to change the number stored in said storage register, said register and said counter each including a plurality of flip flops each having a "0" output and a "1" output, said coincidence gate including a first AND gate for each significant digit to be used, each said first AND gate having an input connected from a "0" output of a corresponding flip flop representing one significant digit in said storage register and another input connected from the "0" output of a corresponding flip flop representing the same significant digit in said counter, said coincidence gate also including a second AND gate for each significant digit to be used, each said second AND gate having an input connected from the "1" output of a corresponding flip flop representing one significant digit in said storage register and another input connected from a "1" output of a corresponding flip flop representing the same significant digit in said counter, each of said first and second AND gates having an output, said coincidence gate including an OR gate for each pair of AND gates corresponding to one significant digit, each OR gate having an output and inputs connected from the outputs of each corresponding pair of AND gates, said coincidence gate also including a third AND gate having an output and an input from each OR gate output, said third AND gate output being connected to said counter reset input, said coincidence output signal appearing at the output of said third AND gate.
Claim 2
Dependent Claim
376 words
A rate divider comprising: a storage register having a plurality of stages; a counter having a plurality of stages and having count and reset inputs; a coincidence gate having an output and having plural inputs connected from the stages of both said storage register and said counter for producing an output pulse at said output thereof when the number stored in said counter becomes equal to the number stored in said storage register; clock means having an output signal frequency and an output connected to said counter count input, said coincidence gate having an output signal of a frequency equal to the clock means frequency divided by the number stored in said register, said coincidence gate also being connected to the reset input of said counter; and means to change the number stored in said storage register, said register and said counter each including a plurality of flip flops each having a "0" output and a "1" output, said coincidence gate including a first AND gate for each significant digit to be used, each said first AND gate having an input connected from a "0" output of a corresponding flip flop representing one significant digit in said storage register and another input connected from the "0" output of a corresponding flip flop representing the same significant digit in said counter, said coincidence gate also including a second AND gate for each significant digit to be used, each said second AND gate having an input connected from the "1" output of a corresponding flip flop representing one significant digit in said storage register and another input connected from a "1" output of a corresponding flip flop representing the same significant digit in said counter, each of said first and second AND gates having an output, said coincidence gate including an OR gate for each pair of AND gates corresponding to one significant digit, each OR gate having an output and inputs connected from the outputs of each corresponding pair of AND gates, said coincidence gate also including a third AND gate having an output and an input from each OR gate output, said third AND gate output being connected to said counter reset input, said coincidence output signal appearing at the output of said third AND gate.