Frequency memory apparatus

Claim 2

A frequency memory comprising an amplifier and a delay line coupled in an oscillatory loop; means for applying an input pulse of periodic signal to said loop, said loop responding thereto to recirculate said pulse; means for correlating said input pulse with the first recirculated version of itself; and means responsive to said correlating means to adjust the phase delay of said loop in a direction to optimize the memory output power at the frequency of said periodic signal.

Claim 3

Memory apparatus as set forth in claim 1 wherein the delay interval of said delay line is less than the width of said input pulse whereby said correlation occurs prior to the termination of said input pulse.

Claim 4

Memory apparatus as set forth in claim 2 wherein said correlation means includes a signal combining means for combining said input pulse and said first recirculated version so as to produce first and second output signals which are 180° out of phase with one another, a comparator for comparing said first output signal of the signal combiner with a delayed version of itself to produce a bivalued phase correction signal; and wherein said phase adjusting means responds to said phase correction signal to couple either said first or said second output signal of the signal combiner in said oscillatory loop in accordance with the value of said phase correction signal.

Claim 5

Memory apparatus as set forth in claim 3 wherein said phase adjusting means includes a switch operable to couple either the first or the second output signal of said signal combiner means in said oscillatory loop; and a control circuit responsive to said phase correction signal to control the switching position of said switch.

Claim 6

Memory apparatus as set forth in claim 4 wherein said phase correlation signal has a first of its two values prior to the receipt of said input pulse and the second of its two values whenever the phase difference between the first input pulse and the first recirculated version is greater than a predetermined amount; and wherein said control circuit responds to said first and second phase correction signal values to place said switch in its second and first switching positions, respectively.

Claim 7

Memory apparatus as set forth in claim 5 and further including means for sampling the output of said comparator during the time that the input pulse and the first recirculated version overlap one another in time such that the phase correction signal has its first value at all times except for the sample period and either its first or second value during the sample period; and wherein said control circuit includes means for storing the occurrence of the second value of the phase correction signal during the sample period; and gating means responsive to said phase correction signal and to said storage means for controlling the switching position of said switch.

Claim 8

Memory apparatus as set forth in claim 2 wherein said correlating means produces a plurality of phase correction signals; and wherein said phase adjusting means responds to said phase correction signals to adjust the phase delay of said loop in increments of 90°.

Claim 9

Memory apparatus as set forth in claim 7 wherein said correlating means includes first and second signal combining means for combining said input pulse with said first recirculated version and with said first recirculated version shifted 90° in phase, respectively, each said signal combining means producing first and second output signals 90° out of phase with one another; comparator means for comparing the second output signal of said first signal combiner with each of the first and second output signals of the second signal combiner to produce first and second bivalued comparator output signals, respectively; and gating means responsive to said comparator output signals for producing first and second ones of said phase correction signals; and wherein the first output signal of said first signal combining means is coupled in said oscillatory loop.

Claim 10

Memory apparatus as set forth in claim 8 wherein said phase adjusting means includes a four state phase shifter coupled within said oscillatory loop; and a control circuit responsive to said phase correction signals to control the phase state of said phase shifter.

Claim 11

Memory apparatus a set forth in claim 9 wherein said gating means includes a first gating network for producing said first phase comparison signal as a function only of said first comparator output signal; and a second gating network for producing said second phase correction signal whenever the first and second comparator output signals are identical in value.

Claim 12

Memory apparatus as set forth in claim 10 wherein said four state phase shifter includes first and second shifting networks connected in cascade, the first phase shifting network having phase shift positions of 0° and 180° and the second phase shifting network having phase shift positions of 0° and 90° and wherein said control circuit responds to the first and second values of said first phase correction signal to place said first network in the 0° and 180° phase shift positions, respectively, and further responds to the first and second values of said second phase correction signal to place said second network into its 0° and 90° phase shift position, respectively.

Claim 13

Memory apparatus as set forth in claim 11 and further including means for sampling said first and second gating networks during the time that the input pulse and the first recirculated version overlap one another in time such that the first and second phase correction signals have their first values at all times except for the sample period and either their first or second values during the sample period; and wherein said control circuit includes first and second means for storing the occurrences of the second values of the first and second phase correction signals, respectively, during the sample period; and first and second gating circuits responsive to said first and second phase correction signals and to said first and second storage means, respectively, for controlling the phase shift positions of said first and second phase shifting networks, respectively.

Claim 14

Memory apparatus as set forth in claim 2 and further including means responsive to the power level of the input pulse to adjust the signal attenuation within said loop during the first recirculation so that the power level of the first recirculated pulse more nearly corresponds to the power level of the input pulse.

Claim 15

Memory apparatus as set forth in claim 13 wherein said loop attenuating adjusting means includes a multi-state attenuator coupled within said loop; and an attenuator control network responsive to the power level of said input signal to place said loop attenuator in an attenuation state which allows the power level of the first recirculated pulse to correspond to the power level of the input pulse.

Claim 16

Memory apparatus as set forth in claim 2 and further including means responsive to said input pulse for preventing the first recirculated pulse from again traversing the loop.

Claim 17

Memory apparatus as set forth in claim 15 wherein said prevention means includes a first switch operative in first and second positions to couple the recirculated pulses from the output of said phase adjusting means to either a first dummy load or into said loop for recirculation, respectively; a second switch operative in first and second positions to couple the output of the phase adjusting means to either said correlating means or to a second dummy load, respectively; and a switch control network responsive to said input pulse to place said first and second switches in their respective first positions for the duration of said input pulse and to thereafter place said first and second switches into their respective second positions.

Claim 18

Memory apparatus as set forth in claim 2 wherein the aforesaid delay line is hereafter referred to as the first delay line; and further including a second delay line having a delay which is longer than that of the first delay line; first switching means responsive to said input pulse for loading said second delay line with the signal stored in said loop after said correlation occurs; and second switching means responsive to said input pulse for decoupling said first delay line from and coupling said second delay line into said loop after said second delay line has been loaded.