US3961165A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Image information transfer device
Assignee: Olympus Corp
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Filing: 1974-06-20
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Granted: 1976-06-01
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Expires: 1994-06-20
Abstract
Abstract An image informaton transfer device which is applicable to an image information transmission apparatus which makes use of a motor driven scanning element and is liable to be subjected to jitter by variation in speed of the motor. The device comprises a first shift register, a second shift register and a control part, whereby an information required to be transferred is stored between the most significant digit and the least significant digit without forming any vacancy therebetween.
Inventors
- 👤 Kenji Fukuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:03
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/04; H04N1/047; H04N1/053
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
361 words
An image information transfer device comprising: first means comprising a shift register 1 including a plurality of stages arranged in sequential order for memorizing input image information data; second means comprising a shift register 2 having a plurality of stages which are the same in number as said stages of said first means and are arranged in sequential order for memorizing data representing a memorized condition in each stage of said first means; means for causing the first of said stages of said second means to memorize data representing that data is present in a first of the stages of said first means when said input image information data is memorized in said first stage of said first means and memorize data representing that said input image information data is absent in said first stage of said first means when said input image information data is not memorized in said first stage of said first means (first clock pulse generating source 7, AND1 and connections); comparing means for periodically comparing data representing a memorized condition of a given stage of said second means with data representing a memorized condition of a stage arranged next to said given stage (AND2, AND3, AND4... and connections); means for transferring input image information data memorized at that stage of said first means which corresponds to said given stage of said second means to a stage next to that stage of said first means when said comparing means detects that said data representing said memorized condition of said stage arranged next to said given stage of said second means represents that data is absent and simultaneously transferring said data representing said memorized condition of said given stage of said second means to said stage arranged next to said given stage (second clock pulse generating source 8, AND2, AND3, AND4 and connections); and means for reading out an input image information data memorized at the final stage of said first means when data representing a memorized condition in the final stage of said second means is data representing that a data is present in the final stage (third clock pulse generating source 9, AND5, FF5 and connections).
Claim 2
Dependent Claim
361 words
An image information transfer device comprising: first means comprising a shift register 1 including a plurality of stages arranged in sequential order for memorizing input image information data; second means comprising a shift register 2 having a plurality of stages which are the same in number as said stages of said first means and are arranged in sequential order for memorizing data representing a memorized condition in each stage of said first means; means for causing the first of said stages of said second means to memorize data representing that data is present in a first of the stages of said first means when said input image information data is memorized in said first stage of said first means and memorize data representing that said input image information data is absent in said first stage of said first means when said input image information data is not memorized in said first stage of said first means (first clock pulse generating source 7, AND1 and connections); comparing means for periodically comparing data representing a memorized condition of a given stage of said second means with data representing a memorized condition of a stage arranged next to said given stage (AND2, AND3, AND4... and connections); means for transferring input image information data memorized at that stage of said first means which corresponds to said given stage of said second means to a stage next to that stage of said first means when said comparing means detects that said data representing said memorized condition of said stage arranged next to said given stage of said second means represents that data is absent and simultaneously transferring said data representing said memorized condition of said given stage of said second means to said stage arranged next to said given stage (second clock pulse generating source 8, AND2, AND3, AND4 and connections); and means for reading out an input image information data memorized at the final stage of said first means when data representing a memorized condition in the final stage of said second means is data representing that a data is present in the final stage (third clock pulse generating source 9, AND5, FF5 and connections).
Claim 3
Dependent Claim
171 words
An image information transfer device as claimed in claim 1, said device further comprising a plurality of information transfer unit circuits connected in cascade, each of said information transfer unit circuits comprising a set of information memories composed of a first information memory capable of writing in a first information by means of a write-in instruction pulse or erasing said first information by means of an erase instruction pulse and a second information memory capable of writing in or erasing a second information at the same time as said write-in or erasure effected by said first information memory, and a gate circuit adapted to be operated upon receipt of a clock pulse to deliver a write-in instruction to said set of information memories when said second information memory is at its first condition and deliver an erase instruction to another set of information memories which are the same as said one set of information memories when said second information memory is changed over from said first condition to a second condition.
Claim 4
Dependent Claim
161 words
An image information transfer device as claimed in claim 1, said device further comprising a plurality of information transfer unit circuits connected in cascade, each of said information transfer unit circuits comprising a set of information memories composed of a first information memory capable of writing in and transferring first information by means of a transfer instruction pulse and a second information memory capable of writing in and transfering second information at the same time as said write-in and transfer effected by said first information memory, an OR circuit capable of detecting a first condition of said second information memory or a first condition of a second information memory of another set of information memories which are the same as said set of information memories and delivering an output, and an AND circuit capable of passing and controlling a clock pulse by means of the output from said OR circuit and delivering a transfer instruction to said set of informations memories.
References Cited (Backward Citations)
US3209330A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-01 | 1979-12-01 | 1980-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-01 | 1983-12-01 | 1984-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-01 | 1987-12-01 | 1988-06-01 | $7700.00 | Window Closed / Lapsed |