US3956644A
Expired / Lapsed
US
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Integral cycle, precise zero voltage switch
Assignee: ELMA ENGR
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Filing: 1974-10-10
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Granted: 1976-05-11
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Expires: 1994-10-10
Abstract
Abstract Alternating current from a source is supplied to a load through a thyristor whose gate electrode is controlled by the output from a zero voltage switch. The zero voltage switch is enabled by the output of a flip-flop beginning at the simultaneous occurrence of a command input and a clock signal input to the flip-flop. The clock signal input is generated just before the beginning of each half cycle of a predetermined polarity of the alternating current so that integral cycling is achieved without delayed switching which would produce current spikes.
Inventors
- 👤 Bhagvantrao G. Zambre
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:31
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/78; H03K17/79; H03K17/13; H03K17/136; Y; Y10; Y10S; Y10S323/00; Y10S323/902
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
117 words
An integral cycle, precise zero voltage switch for supplying alternating current from an external source to a load comprising means for generating a command signal, means for generating a clock signal just before the beginning of each half cycle of a predetermined polarity of the alternating current, bistable logic means responsive to the command and clock signals for producing a logic signal beginning at the simultaneous occurrence of the command and clock signals and ending with the occurrence of the clock signal alone, and switching means for supplying the alternating current to the load beginning and ending from the zero crossing of the alternating current and provided that the switching means is enabled by the logic signal.
Claim 2
Dependent Claim
117 words
An integral cycle, precise zero voltage switch for supplying alternating current from an external source to a load comprising means for generating a command signal, means for generating a clock signal just before the beginning of each half cycle of a predetermined polarity of the alternating current, bistable logic means responsive to the command and clock signals for producing a logic signal beginning at the simultaneous occurrence of the command and clock signals and ending with the occurrence of the clock signal alone, and switching means for supplying the alternating current to the load beginning and ending from the zero crossing of the alternating current and provided that the switching means is enabled by the logic signal.
Claim 3
Dependent Claim
60 words
An integral cycle, precise zero voltage switch as recited in claim 1 wherein the switching means comprises a gate controlled switch connected in series with the load and the alternating current source and a zero voltage switch controlled by the logic signal and the alternating current and having an output connected to the gate electrode of the gate controlled switch.
Claim 4
Dependent Claim
149 words
An integral cycle, precise zero voltage switching control for use with a load and a source of alternating current comprising clock means responsive to the alternating current for producing a clock pulse just before the positive going transition about the zero voltage level of the alternating current, means for supplying a switching command signal, bistable logic means responsive to both the clock pulse and the command signal for producing a logic signal beginning just before the positive half cycle of the alternating current and extending for a complete cycle of the alternating current, provided that the bistable logic means simultaneously receives a command signal and a clock pulse, and zero voltage switch means which is enabled by the logic signal and which conducts alternating current from the source to the load beginning and ending at the zero voltage crossings of the alternating current in response to the logic signal.
Claim 5
Dependent Claim
149 words
An integral cycle, precise zero voltage switching control for use with a load and a source of alternating current comprising clock means responsive to the alternating current for producing a clock pulse just before the positive going transition about the zero voltage level of the alternating current, means for supplying a switching command signal, bistable logic means responsive to both the clock pulse and the command signal for producing a logic signal beginning just before the positive half cycle of the alternating current and extending for a complete cycle of the alternating current, provided that the bistable logic means simultaneously receives a command signal and a clock pulse, and zero voltage switch means which is enabled by the logic signal and which conducts alternating current from the source to the load beginning and ending at the zero voltage crossings of the alternating current in response to the logic signal.
Claim 6
Dependent Claim
88 words
An integral cycle, precise zero voltage switching control as recited in claim 3 wherein the bistable logic means includes a flip-flop having a first input to which the command signal is applied, a second input to which the clock signal is applied, and an output from which the logic signal is derived, the logic signal output being representative of the command signal during a period of time beginning with the simultaneous occurrence of the command and clock signals and ending with the occurrence of the clock signal alone.
Claim 7
Dependent Claim
88 words
An integral cycle, precise zero voltage switching control as recited in claim 4 wherein the zero voltage switch means includes a zero voltage switch which, when enabled by the logic signal, produces even numbers of output pulses symmetrically around the zero voltage crossings of the alternating current, and gate controlled switching means connected in series with the load and the source of alternating current with the gate of the gate controlled switching means being supplied with the output pulses of the zero voltage switch to render it conductive.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-11 | 1979-11-10 | 1980-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-11 | 1983-11-10 | 1984-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-11 | 1987-11-10 | 1988-05-11 | $7700.00 | Window Closed / Lapsed |