US3949296A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Code and generating means for avionics communciations synthesizer
Assignee: NARCO AVIONICS Inc 270 COMMERCE DRIVE FORT WASHINGTON PA A CORP OF
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Filing: 1975-01-23
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Granted: 1976-04-06
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Expires: 1995-01-23
Abstract
Abstract For use in a channel synthesizer utilizing a pulse swallowing phase locked loop, an eight bit code represents the megahertz component of the selected channel. An eight stage shift register is preloaded with the coded version of the selected megahertz component, and exclusive OR logic responsive selectively to the first, third, fifth, and eighth stages generates data for the first stage during the next shift. NAND logic responsive to the various stages detects presence of certain code combinations which are representative of terminal count states. Each terminal count pulse is utilized for comparison with the frequency reference in the phase locked loop, and also in a feedback arrangement to reset the registers to their preloaded states.
Inventors
- 👤 Boyd M. McClaskey
- 👤 John F. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:28
CPC Classifications
H; H04; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
264 words
In an avionics transceiver having transmission channels arrayed in the frequency range 118 through 135 MHz and respectively corresponding reception channels arrayed in the frequency range 130 through 147MHz, pulse frequency division apparatus operable in accordance with the MHz components of a selected transmit-receive channel pair comprising: a shift register having eight sequentially connected stages, the pulse signal to be divided clocking shifts of said register; a first exclusive OR gate responsive to the output states of the first and third ones of said stages; a second exlusive OR gate responsive to the output states of the fifth and eighth ones of said stages; a third exclusive OR gate responsive to said first and second gates; means for inverting the logical output signal of said third gate, and for applying the inverted logical signal to the input of the first of said stages in clocked relationship with the shifting of data between successive sequential stages; means for presetting the output states of each of said stages of said register in accordance with the selected transmit-receive channel pair as follows TRANS RECEIVE STAGES 1 through 8
______________________________________
135 147 00010111
134 146 00001011
133 145 10000101
132 144 11000010
131 143 01100001
130 142 10110000
129 141 11011000
128 140 11101100
127 139 01110110
126 138 00111011
125 137 00011101
124 136 10001110
123 135 11000111
122 134 11100011
121 133 01110001
120 132 10111000
119 131 01011100
118 130 00101110;
______________________________________ and means for producing an output pulse upon occurrence of logical states in said register of 11110000 for transmission and 11101111 for reception.
Claim 2
Dependent Claim
264 words
In an avionics transceiver having transmission channels arrayed in the frequency range 118 through 135 MHz and respectively corresponding reception channels arrayed in the frequency range 130 through 147MHz, pulse frequency division apparatus operable in accordance with the MHz components of a selected transmit-receive channel pair comprising: a shift register having eight sequentially connected stages, the pulse signal to be divided clocking shifts of said register; a first exclusive OR gate responsive to the output states of the first and third ones of said stages; a second exlusive OR gate responsive to the output states of the fifth and eighth ones of said stages; a third exclusive OR gate responsive to said first and second gates; means for inverting the logical output signal of said third gate, and for applying the inverted logical signal to the input of the first of said stages in clocked relationship with the shifting of data between successive sequential stages; means for presetting the output states of each of said stages of said register in accordance with the selected transmit-receive channel pair as follows TRANS RECEIVE STAGES 1 through 8
______________________________________
135 147 00010111
134 146 00001011
133 145 10000101
132 144 11000010
131 143 01100001
130 142 10110000
129 141 11011000
128 140 11101100
127 139 01110110
126 138 00111011
125 137 00011101
124 136 10001110
123 135 11000111
122 134 11100011
121 133 01110001
120 132 10111000
119 131 01011100
118 130 00101110;
______________________________________ and means for producing an output pulse upon occurrence of logical states in said register of 11110000 for transmission and 11101111 for reception.
Claim 3
Dependent Claim
86 words
Apparatus as described in claim 1 wherein means for producing includes: a first NAND gate responsive to the outputs of the first four of said stages and to the inverted output of the eighth of said stages; a second NAND gate responsive to the outputs of the second, third, and fifth through eighth of said stages; a fourth exclusive OR gate responsive to said NAND gates; and an inverter for producing a signal for energizing resetting by inverting the output of said fourth exclusive OR gate.
Claim 4
Dependent Claim
53 words
Apparatus as described in claim 2 wherein said means for presetting comprises rotatable wafer switch means configured in accordance with said preset code allocations for said transmit-receive channel pairs, and eight contacts spaced in proximity with said wafer switch means, each of said contacts being coupled to a different one of said stages.
Claim 5
Dependent Claim
50 words
Apparatus as described in claim 1, adapted to alternate transmit and receive operations of said transceiver, wherein transmit channels are allocated at 25 KHz. increments between 118 and 136 MHz, and receive channels are allocated to correspond respectively to each transmit channel, but are each 12 MHz. higher in frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-04-06 | 1979-10-06 | 1980-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-04-06 | 1983-10-06 | 1984-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-04-06 | 1987-10-06 | 1988-04-06 | $7700.00 | Window Closed / Lapsed |