US3946362A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Time division multiple transmission control apparatus
Assignee: Mazda Motor Corp
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Filing: 1974-07-12
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Granted: 1976-03-23
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Expires: 1994-07-12
Abstract
Abstract A time division multiple transmission control apparatus which comprises a central processing device for generating a reference timing signal having a predetermined frequency and a time division multiple signal having substantially the same frequency for controlling a plurality of electrical devices during predetermined time periods, terminal processing devices for controlling each electrical device during a different predetermined time period under the control of said reference timing signal and said time division multiple signal and means for generating a phase difference between said reference timing signal and said time division multiple signal.
Inventors
- 👤 Shizuo Sumida
- 👤 Kazuo Nii
- 👤 Hisatsugu Ito
- 👤 Atsushi Ueda
- 👤 Mitsuaki Ishii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:49
CPC Classifications
G; G08; G08C; G08C15/00; G08C15/06; G08C15/12; B; B60; B60R; B60R16/00; B60R16/02; B60R16/03; B60R16/0315
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
297 words
A time division multiple transmission control apparatus comprising: a central processing device comprising a reference timing signal generating circuit to generate reference timing signal pulses and a control signal generating circuit to generate control signal pulses, the reference timing pulse signal and the control pulse signal being of the same frequency, a plurality of electrical devices to be selectively driven, a terminal processing device for each electrical device, each terminal processing device comprising: an address detecting circuit comprising a sychronizing signal division circuit and a timing circuit for generating an address signal pulse, a signal separating circuit for generating a driving signal pulse, a driving circuit, means connecting the synchronizing signal division circuit to the timing circuit, means connecting the timing circuit to the signal separating circuit, means connecting the signal separating circuit to the driving circuit, means connecting the driving circuit to the electrical device, means connecting the reference timing signal generating circuit to the control signal generating circuit, a reference timing signal transmission line connected between the reference timing signal generating circuit and each of the synchronizing signal division circuits as well as each of the timing circuits, a control signal transmission line connected between the control signal generating circuit and each of the synchronizing signal division circuits as well as each of the signal separating circuits, means for delaying the control signal pulses with respect to the reference timing signal pulse to generate a phase difference therebetween so that an address signal pulse with a rising and/or falling delay time appearing at the output of a timing circuit in one of the terminal processing devices will not overlap a subsequent control signal pulse causing generation of an undesirable driving signal pulse at the output of the signal separating circuit in the terminal processing device.
Claim 2
Dependent Claim
297 words
A time division multiple transmission control apparatus comprising: a central processing device comprising a reference timing signal generating circuit to generate reference timing signal pulses and a control signal generating circuit to generate control signal pulses, the reference timing pulse signal and the control pulse signal being of the same frequency, a plurality of electrical devices to be selectively driven, a terminal processing device for each electrical device, each terminal processing device comprising: an address detecting circuit comprising a sychronizing signal division circuit and a timing circuit for generating an address signal pulse, a signal separating circuit for generating a driving signal pulse, a driving circuit, means connecting the synchronizing signal division circuit to the timing circuit, means connecting the timing circuit to the signal separating circuit, means connecting the signal separating circuit to the driving circuit, means connecting the driving circuit to the electrical device, means connecting the reference timing signal generating circuit to the control signal generating circuit, a reference timing signal transmission line connected between the reference timing signal generating circuit and each of the synchronizing signal division circuits as well as each of the timing circuits, a control signal transmission line connected between the control signal generating circuit and each of the synchronizing signal division circuits as well as each of the signal separating circuits, means for delaying the control signal pulses with respect to the reference timing signal pulse to generate a phase difference therebetween so that an address signal pulse with a rising and/or falling delay time appearing at the output of a timing circuit in one of the terminal processing devices will not overlap a subsequent control signal pulse causing generation of an undesirable driving signal pulse at the output of the signal separating circuit in the terminal processing device.
Claim 3
Dependent Claim
124 words
A time division multiple transmission control apparatus in accordance with claim 1 wherein the central processing device comprises a reference timing signal generating circuit comprising an oscillator and a frequency dividing circuit, a control signal generating circuit, a delay flip-flop, means connecting the output of the oscillator to the input of the frequency dividing circuit and to an input of the delay flip-flop, means connecting a first output of the control signal generating circuit to the delay flip-flip and an input of the control signal generating circuit to the reference timing signal transmission line, means connecting the output of the frequency dividing circuit to the reference timing signal transmission line, means connecting the output of the delay flip-flop to the control signal transmission line.
Claim 4
Dependent Claim
22 words
A time division multiple transmission control apparatus in accordance with claim 2 wherein the synchronizing signal division circuit comprises a delay flip-flop.
Claim 5
Dependent Claim
19 words
A time division multiple transmission control apparatus in accordance with claim 1 wherein the phase difference is π/2 radians.
Claim 6
Dependent Claim
82 words
A time division multiple transmission control apparatus in accordance with claim 1 wherein the control signal pulses comprise a synchronizing signal pulse for determining the repeat period of the control signal pulses, the control signal pulses being generated corresponding to either the rising or falling of the reference timing signal pulses, and the synchronizing signal pulse being generated corresponding to the rising or falling of the reference timing signal pulses in a manner opposite to the generation of the control signal pulses.
References Cited (Backward Citations)
US3848231A
Cited
US3852713A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-23 | 1979-09-22 | 1980-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-23 | 1983-09-22 | 1984-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-23 | 1987-09-22 | 1988-03-23 | $7700.00 | Window Closed / Lapsed |