US3946321A
Expired / Lapsed
US
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Digital encoder
Assignee: Motorola Solutions Inc
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Filing: 1974-10-15
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Granted: 1976-03-23
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Expires: 1994-10-15
Abstract
Abstract An oscillator with a ceramic resonator in the feedback circuit for providing a stable continuous signal to a programmable divider each time an enable signal is applied to the oscillator, a read-only memory connected to the programmable divider and operated by timing means, including a counter and a clock, which sequentially switches the memory to cause the programmable divider to divide the output of the oscillator by a different divisor to provide a predetermined sequence of signals, each having a desired frequency.
Inventors
- 👤 Kenneth J. Krolik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:25
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/26; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0307; H03K3/78
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
182 words
A digital encoder comprising: a. an oscillator including a two input logic gate amplifier and a ceramic resonator in a phase changing feedback network connected between an input and an output of said logic gate amplifier and providing a continuous signal during proper energization thereof: b. a programmable divider connected to receive the continuous signal from said oscillator and provide a signal at an output which has a frequency equal to the frequency of the continuous signal divided by a predetermined divisor, said divider having a plurality of inputs for receiving different signals thereon representative of different predetermined divisors; c. memory means including a read-only memory code plug having a plurality of outputs connected to the plurality of inputs of said programmable divider and a plurality of corresponding inputs, said memory means providing signals on each of the plurality of outputs representative of a different predetermined divisor in response to an activating signal being applied to the corresponding input; and d. timing means connected to the plurality of inputs of said memory means for providing activating signals thereto in a predetermined sequence.
Claim 2
Dependent Claim
182 words
A digital encoder comprising: a. an oscillator including a two input logic gate amplifier and a ceramic resonator in a phase changing feedback network connected between an input and an output of said logic gate amplifier and providing a continuous signal during proper energization thereof: b. a programmable divider connected to receive the continuous signal from said oscillator and provide a signal at an output which has a frequency equal to the frequency of the continuous signal divided by a predetermined divisor, said divider having a plurality of inputs for receiving different signals thereon representative of different predetermined divisors; c. memory means including a read-only memory code plug having a plurality of outputs connected to the plurality of inputs of said programmable divider and a plurality of corresponding inputs, said memory means providing signals on each of the plurality of outputs representative of a different predetermined divisor in response to an activating signal being applied to the corresponding input; and d. timing means connected to the plurality of inputs of said memory means for providing activating signals thereto in a predetermined sequence.
Claim 3
Dependent Claim
41 words
A digital encoder as claimed in claim 1 wherein the timing means includes a counter with a plurality of outputs connected to the inputs of the memory means and a source of clock pulses connected to an input of said counter.
Claim 4
Dependent Claim
51 words
A digital encoder as claimed in claim 2 wherein an output of the counter is connected to one input of the logic gate amplifier for enabling the oscillatory signal to be applied to said programmable divider during the time that activating signals are being applied to inputs of the memory means.
Claim 5
Dependent Claim
224 words
A digital encoder comprising: a. an oscillator including a logic gate amplifier having two inputs and an output, one of said inputs being adapted to receive an enabling signal thereon, a feedback network connected between the output and the other input of said logic gate amplifier and having attenuation and phase characteristics sufficient for providing sustained oscillations when an enabling signal is applied to the one input of said logic gate amplifier, and said feedback network including a pi network having a ceramic resonator therein providing a continuous signal during proper energization thereof; b. a programmable divider connected to receive the continuous signal from said oscillator and provide a signal at an output which has a frequency equal to the frequency of the continuous signal divided by a predetermined divisor, said divider having a plurality of inputs for receiving different signals thereon representative of different predetermined divisors; c. memory means having a plurality of outputs connected to the plurality of inputs of said programmable divider and a plurality of corresponding inputs, said memory means providing signals on each of the plurality of outputs representative of a different predetermined divisor in response to an activating signal being applied to the corresponding input; and d. timing means connected to the plurality of inputs of said memory means for providing activating signals thereto in a predetermined sequence.
Claim 6
Dependent Claim
224 words
A digital encoder comprising: a. an oscillator including a logic gate amplifier having two inputs and an output, one of said inputs being adapted to receive an enabling signal thereon, a feedback network connected between the output and the other input of said logic gate amplifier and having attenuation and phase characteristics sufficient for providing sustained oscillations when an enabling signal is applied to the one input of said logic gate amplifier, and said feedback network including a pi network having a ceramic resonator therein providing a continuous signal during proper energization thereof; b. a programmable divider connected to receive the continuous signal from said oscillator and provide a signal at an output which has a frequency equal to the frequency of the continuous signal divided by a predetermined divisor, said divider having a plurality of inputs for receiving different signals thereon representative of different predetermined divisors; c. memory means having a plurality of outputs connected to the plurality of inputs of said programmable divider and a plurality of corresponding inputs, said memory means providing signals on each of the plurality of outputs representative of a different predetermined divisor in response to an activating signal being applied to the corresponding input; and d. timing means connected to the plurality of inputs of said memory means for providing activating signals thereto in a predetermined sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-23 | 1979-09-22 | 1980-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-23 | 1983-09-22 | 1984-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-23 | 1987-09-22 | 1988-03-23 | $7700.00 | Window Closed / Lapsed |