False triggering prevention circuit

Claim 2

A pulse circuit comprising: input circuit means for receiving input pulses; output circuit means for providing output pulses; pulse extractor means for extracting a predetermined number of initial ones of said input pulses interconnecting said input circuit means and said output circuit means, said pulse extractor means being nonresponsive to said predetermined number of initial ones of said input pulses applied thereto and responsive to input pulses subsequent to said predetermined number of initial ones of said input pulses for rendering said output means operative to provide output pulses in response to input pulses following said initial ones of said input pulses; and timing means coupled to said pulse extractor means and to said input circuit means, said timing means being responsive to one of said input pulses for rendering said pulse extractor means operative to extract a number of subsequent input pulses equal in number to said predetermined number upon the elapse of a predetermined time interval following the receipt of said one of said input pulses.

Claim 3

A pulse circuit as recited in claim 1 further including pulse shaping means electrically coupled to said input circuit means, said pulse shaping means including means for providing pulses having a fixed duration in response to input pulses having a duration less than said fixed duration, and for providing pulses having a duration equal to the duration of said input pulses in response to input pulses having a duration greater than said fixed duration.

Claim 4

A pulse circuit as recited in claim 1 wherein said pulse extractor means includes means responsive to pulses applied to said input means for providing an enabling signal following the receipt of said predetermined number of initial input pulses.

Claim 5

A pulse circuit as recited in claim 3 further including gating means responsive to said enabling signal providing means for providing pulses to said output circuit means in response to said input pulses only upon receipt of said enabling signal.

Claim 6

A pulse circuit as recited in claim 4 wherein said enabling signal providing means includes a single flip-flop.

Claim 7

A pulse circuit as recited in claim 5 wherein said enabling signal providing means includes a second flip-flop connected to said flip-flop.

Claim 8

A pulse circuit as recited in claim 3 wherein said timing means includes a timing monostable multivibrator connected to said pulse extractor means for resetting said pulse extractor means to terminate said enabling signal following the elapse of said predetermined time interval.

Claim 9

A pulse circuit as recited in claim 7 further including pulse shaping means comprising a pulse shaping monostable multivibrator means for providing fixed duration pulses in response to input pulses, and gating means, said gating means being responsive to said input means for providing an output pulse having a duration equal to the longer of said input pulse and said fixed duration pulse.

Claim 10

In an alarm system responsive to a predetermined first condition for providing a first condition indicative signal having a predetermined minimum number of pulses within a predetermined time interval, and to a second condition for providing a second condition indicative signal having fewer than said predetermined number of pulses within said predetermined time interval, said alarm system being responsive to said first and second condition indicative signal for providing an alarm signal, a circuit for rendering said alarm system nonresponsive to said second condition indicative signal, comprising: means for receiving said first and second condition indicative signals; means for providing a timing signal representative of said predetermined time interval; means connected to said receiving means and to said timing signal providing means and responsive thereto for providing a first output signal in response to the receipt of said timing signal and said first condition indicative signal and for providing a second output signal in response to the receipt of said timing signal and said second condition indicative signal, said output signal providing means including counting means responsive to the receipt of said predetermined minimum number of pulses for providing said first output signal; and gating means coupled to said output signal providing means and said receiving means, said gating means being responsive to said output signal providing means for passing therethrough those pulses of said first condition indicative signal exceeding said predetermined minimum number of pulses wherein said timing signal providing means is coupled to said counting means for resetting said counting means said predetermined time interval following the receipt of one of the pulses of one of said first and second condition indicative signals.

Claim 11

In an alarm system responsive to a predetermined first condition for providing a first condition indicative signal having a predetermined minimum number of pulses within a predetermined time interval, and to a second condition for providing a second condition indicative signal having fewer than said predetermined number of pulses within said predetermined time interval, said alarm system being responsive to said first and second condition indicative signal for providing an alarm signal, a circuit for rendering said alarm system nonresponsive to said second condition indicative signal, comprising: means for receiving said first and second condition indicative signals; means for providing a timing signal representative of said predetermined time interval; means connected to said receiving means and to said timing signal providing means and responsive thereto for providing a first output signal in response to the receipt of said timing signal and said first condition indicative signal and for providing a second output signal in response to the receipt of said timing signal and said second condition indicative signal, said output signal providing means including counting means responsive to the receipt of said predetermined minimum number of pulses for providing said first output signal; and gating means coupled to said output signal providing means and said receiving means, said gating means being responsive to said output signal providing means for passing therethrough those pulses of said first condition indicative signal exceeding said predetermined minimum number of pulses wherein said timing signal providing means is coupled to said counting means for resetting said counting means said predetermined time interval following the receipt of one of the pulses of one of said first and second condition indicative signals.

Claim 12

A circuit as recited in claim 9 further including pulse shaping means coupled to said receiving means for extending to said predetermined length the length of pulses that are shorter than said predetermined length.

Claim 13

A pulse circuit comprising: input circuit means for receiving input pulses; output circuit means for providing output pulses; pulse extractor means interconnecting said input circuit means and said output circuit means, said pulse extractor means being nonresponsive to a number of initial pulses applied thereto and responsive to input pulses subsequent to said predetermined number of initial input pulses for rendering said output means operative to provide output pulses in response to input pulses following said initial input pulses; and pulse shaping means interposed between said input circuit means and said output circuit means, said pulse shaping means including means for providing pulses having a fixed duration in response to input pulses having a duration less than said fixed duration, and for providing pulses having a duration equal to the duration of said input pulses in response to input pulses having a duration greater than said fixed duration.

Claim 14

A pulse circuit comprising: input circuit means for receiving input pulses; output circuit means for providing output pulses; pulse extractor means interconnecting said input circuit means and said output circuit means, said pulse extractor means being nonresponsive to a number of initial pulses applied thereto and responsive to input pulses subsequent to said predetermined number of initial input pulses for rendering said output means operative to provide output pulses in response to input pulses following said initial input pulses; and pulse shaping means interposed between said input circuit means and said output circuit means, said pulse shaping means including means for providing pulses having a fixed duration in response to input pulses having a duration less than said fixed duration, and for providing pulses having a duration equal to the duration of said input pulses in response to input pulses having a duration greater than said fixed duration.