US3944925A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-locked loop transceiver having automatic frequency offset selectability
Assignee: Motorola Solutions Inc
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Filing: 1974-08-05
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Granted: 1976-03-16
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Expires: 1994-08-05
Abstract
Abstract This specification discloses a frequency synthesizer or phase-locked loop transceiver operating from a reference oscillator source, F REF . A single phase-locked loop system for the transceiver includes counter means located in a feedback path connected between a voltage controlled oscillator (VCO) and a digital phase detector. The counter is preset to a predetermined number N for generating a frequency representation ##EQU1## The counter means includes logic and decoding circuitry for automatically modifying the ##EQU2## signal representation by a factor M for generating a feedback signal F F , where F F is ##EQU3## The feedback signal representation ##EQU4## is applied to the digital phase detector for generating a transmit or receive signal F OUT, where F OUT = F REF .sup.(N ± M).
Inventors
- 👤 Jon M. De Laune
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:28
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/195; H04; H04B; H04B1/00; H04B1/38; H04B1/40; H04B1/403; H04B1/405
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
175 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said first predetermined frequency varying signal a predetermined amount in response to a reference signal F REF comprising: a. a phase-locked loop means having a feed forward path including a phase detector and a voltage controlled oscillator and a feedback path coupled between a first input terminal means and an output terminal means and being responsive to the signal F REF for generating the signal F OUT at said output terminal; b. said phase-locked means further including counter means coupled between said input and said output terminals in said feedback path; c. said counter means including means for programming a selective digital representation of N and means for generating the offset digital frequency M and storing a digital frequency representation N ± M said counter being responsive to F OUT and said digital representation N ± M for generating F F , where F F is ##EQU8##
Claim 2
Dependent Claim
175 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said first predetermined frequency varying signal a predetermined amount in response to a reference signal F REF comprising: a. a phase-locked loop means having a feed forward path including a phase detector and a voltage controlled oscillator and a feedback path coupled between a first input terminal means and an output terminal means and being responsive to the signal F REF for generating the signal F OUT at said output terminal; b. said phase-locked means further including counter means coupled between said input and said output terminals in said feedback path; c. said counter means including means for programming a selective digital representation of N and means for generating the offset digital frequency M and storing a digital frequency representation N ± M said counter being responsive to F OUT and said digital representation N ± M for generating F F , where F F is ##EQU8##
Claim 3
Dependent Claim
89 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said first predetermined frequency varying signal a predetermined amount in response to a reference signal F REF as in claim 1 wherein: a. said counter means comprises a programmable counter means having first input means for storing a digital representation N and second input means for receiving a digital representation of M for altering paid programmable counter to N ± M.
Claim 4
Dependent Claim
74 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said first predetermined frequency varying signal a predetermined amount in response to a reference signal F REF as in claim 1 wherein: a. said counter means comprises a plurality of stages and decoding logic means coupled thereto and being responsive to a digital representation of N.
Claim 5
Dependent Claim
98 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said first predetermined frequency signal a predetermined amount in response to a reference signal F REF as in claim 3 wherein: a. said decoding logic means includes a plurality of logic gates and switch means coupled thereto, b. said switch means being responsive to said digital representation of M for generating gating signals for controlling said plurality of logic gates in order to vary the value of N ± M.
Claim 6
Dependent Claim
70 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said first predetermined frequency signal a predetermined amount in response to a reference signal F REF as in claim 4 wherein: a. said decoding logic means further includes memory means coupled to said switch means for varying said digital representation of M.
Claim 7
Dependent Claim
66 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said first predetermined frequency signal a predetermined amount in response to a reference signal F REF as in claim 1 further comprising: a. transmitter and receiver means coupled to said phase-locked loop means for providing a transceiver system.
Claim 8
Dependent Claim
66 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said first predetermined frequency signal a predetermined amount in response to a reference signal F REF as in claim 2 further comprising: a. transmitter and receiver means coupled to said phase-locked loop means for providing a transceiver system.
Claim 9
Dependent Claim
66 words
A phase-locked loop system for generating an output signal F OUT from any first predetermined frequency varying signal N and any second frequency varying signal M offset from said frist predetermined frequency signal a predetermined amount in response to a reference signal F REF as in claim 4 further comprising: a. transmitter and receiver means coupled to said phase-locked loop means for providing a transceiver system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-16 | 1979-09-15 | 1980-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-16 | 1983-09-15 | 1984-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-16 | 1987-09-15 | 1988-03-16 | $7700.00 | Window Closed / Lapsed |