Abstract A digital launch sequence timing network in a single rail launcher which interprets signals from the aircraft and generates the signals necessary to automatically prepare and launch a missile. In order to launch the missile, a number of signals must be sent from the launcher to the missile in a particular time sequence. The launcher must first send an activate pulse to the missile battery which lasts for a predetermined amount of time, until the missile battery reaches its operational condition. Next, the launcher delivers a pulse to activate the missile rocket motor to provide the propulsion needed by the missile when it leaves the launcher. The preparation steps needed to prepare and launch the missile must take place in an exact time sequence which is provided by the digital timing network, composed of several shift registers. The single rail launcher is used for carrying and launching the maverick missile.
A digital launch sequence timer in a single rail launcher for controlling the timing of the sequence of events necessary to launch the missile having a battery and a motor, and means under the control of the aircraft pilot for producing a launch signal for starting the timing sequence, wherein the improvement comprises: a NAND gate for receiving said launch signal, said NAND gate having an output; a first shift register being connected to said output of said NAND gate, said register having two outputs; said first output of first register for delivering a pulse of predetermined duration to activate the missile battery; a second shift register having a motor firing signal output, said second shift register having its input connected to said second output of said first register, said second shift register delaying the initiation of said firing signal by a predetermined period; said second register having an output carrying the delayed firing initiation signal; and a third shift register connected to said output of said second register for timing the duration of said launch pulse signal to said motor.
Claim 2
Dependent Claim
181 words
A digital launch sequence timer in a single rail launcher for controlling the timing of the sequence of events necessary to launch the missile having a battery and a motor, and means under the control of the aircraft pilot for producing a launch signal for starting the timing sequence, wherein the improvement comprises: a NAND gate for receiving said launch signal, said NAND gate having an output; a first shift register being connected to said output of said NAND gate, said register having two outputs; said first output of first register for delivering a pulse of predetermined duration to activate the missile battery; a second shift register having a motor firing signal output, said second shift register having its input connected to said second output of said first register, said second shift register delaying the initiation of said firing signal by a predetermined period; said second register having an output carrying the delayed firing initiation signal; and a third shift register connected to said output of said second register for timing the duration of said launch pulse signal to said motor.