Signal averaging circuit

Claim 2

A circuit for producing an output signal representing a running average of a continuous input signal comprising: an input for said continuous input signal; a pulse forming and shaping means responsive to said continuous input signal for producing a train of output pulses; a pulse accumulating means responsive to said output pulse train for accumulating a predetermined number of pulses representing said running average output signal whereby the most recent pulse replaces the oldest pulse in said pulse accumulating means; and a clock means for controlling said pulse forming and shaping means and said pulse accumulating means.

Claim 3

A circuit according to claim 1 wherein said continuous input signal is cyclic.

Claim 4

a circuit according to claim 1 wherein said continuous input signal is a pulse train.

Claim 5

A circuit according to claim 1 wherein said pulse forming and shaping means includes means for amplifying said continuous input signal, means for shaping said amplified signal, means for forming said shaped signal into a square wave pulse train and means responsive to said square wave pulse train and to said clock means for producing said train of output pulses with a selected pulse width.

Claim 6

A circuit according to claim 4 wherein said means for amplifying includes a voltage comparator having inverting and noninverting inputs connected to said input for said continuous input signal and an output connected to said means for shaping.

Claim 7

A circuit according to claim 4 wherein said clock means generates a high frequency pulse train and said means for producing said train of output pulses with a selected pulse width includes a first counting means connected to said clock means for counting a first predetermined number of said high frequency pulse train pulses and a second counting means for counting a second predetermined number of said high frequency pulse train pulses whereby the frequency of said output pulses is determined by multiplying the frequency of said square wave times a fraction comprised of said second predetermined number as the numerator and said first predetermined number as the denominator.

Claim 8

A circuit according to claim 1 wherein said pulse accumulating means includes storage means for said train of output pulses, counting means for counting the number of pulses in said storage means and means for coupling said storage means and said counting means.

Claim 9

A circuit according to claim 7 wherein said storage means includes a one bit temporary storage buffer for said output pulses.

Claim 10

A circuit according to claim 8 wherein said temporary storage buffer is a flip flop which has a first output state when set by one of said output pulses and a second output state when reset by a count/circulate signal from said clock means.

Claim 11

A circuit according to claim 9 wherein said storage means includes a recirculating shift register with a capacity of N bits which reads the output state of said temporary storage buffer in response to said count/circulate signal and stores a signal representing said output state by replacing the oldest of said N bits in storage.

Claim 12

A circuit according to claim 10 wherein said recirculating shift register produces an output signal representing said N bits in storage in time-sequenced order in response to a clock signal from said clock means

Claim 13

A circuit according to claim 11 wherein said counting means includes three decade counters connected in series for producing said running average output signal in binary form.

Claim 14

A circuit for producing a first and a second output signal representing a running average of a first and a second continuous input signal respectively comprising: a first input for said first continuous input signal; a first pulse forming and shaping means responsive to said first continuous input signal for producing a first train of output pulses; a first pulse accumulating means responsive to said first train of output pulses for accumulating a first predetermined number of pulses representing said first running average output signal whereby the most recent pulse replaces the oldest pulse in said pulse accumulating means; a second input for said continuous input signal; a second pulse forming and shaping means responsive to said second continuous input signal for producing a second train of output pulses; a second pulse accumulating means responsive to said second train of output pulses for accumulating a second predetermined number of pulses representing said second running average output signal whereby the most recent pulse replaces the oldest pulse in said pulse accumulating means; and a clock means for controlling said first and second pulse forming and shaping means and said first and second pulse accumulating means.

Claim 15

A circuit for producing a first and a second output signal representing a running average of a first and a second continuous input signal respectively comprising: a first input for said first continuous input signal; a first pulse forming and shaping means responsive to said first continuous input signal for producing a first train of output pulses; a first pulse accumulating means responsive to said first train of output pulses for accumulating a first predetermined number of pulses representing said first running average output signal whereby the most recent pulse replaces the oldest pulse in said pulse accumulating means; a second input for said continuous input signal; a second pulse forming and shaping means responsive to said second continuous input signal for producing a second train of output pulses; a second pulse accumulating means responsive to said second train of output pulses for accumulating a second predetermined number of pulses representing said second running average output signal whereby the most recent pulse replaces the oldest pulse in said pulse accumulating means; and a clock means for controlling said first and second pulse forming and shaping means and said first and second pulse accumulating means.

Claim 16

A circuit according to claim 13 including means for time delaying said first average output signal relative to said second average output signal.

Claim 17

A circuit according to claim 14 wherein said means for delaying includes a latch and means for clocking said latch.

Claim 18

A circuit for producing an output signal representing a running average of a continuous input signal comprising: an input for said continuous signal; means for sampling said continuous input signal; means for accumulating and separately storing each of a predetermined number N of the N most recent samples from said sampling means representing said running average output signal whereby the most recent sample replaces the oldest sample in said sample accumulating means; means responsive to said accumulated samples for generating said running average output signal; and a clock means for controlling said sampling means and said sample accumulating means.

Claim 19

A circuit for producing an output signal representing a running average of a continuous input signal comprising: an input for said continuous signal; means for sampling said continuous input signal; means for accumulating and separately storing each of a predetermined number N of the N most recent samples from said sampling means representing said running average output signal whereby the most recent sample replaces the oldest sample in said sample accumulating means; means responsive to said accumulated samples for generating said running average output signal; and a clock means for controlling said sampling means and said sample accumulating means.

Claim 20

A circuit according to claim 16 wherein said sample accumulating means is a shift register.