US3934096A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-frequency signal receiving circuit
Assignee: Hitachi Ltd
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Filing: 1973-04-27
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Granted: 1976-01-20
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Expires: 1993-04-27
Abstract
Abstract A multi-frequency signal receiving circuit comprising a check circuit for discriminating the existence of a predetermined number of signal frequencies constituting a signal to produce an output, a timing circuit for delaying the output of the check circuit, a rectifying circuit for receiving the signal to detect the received signal energy and produce an output, a timing circuit for delaying the output of the rectifying circuit, an AND gate circuit for receiving the outputs of the two timing circuits to produce an output, and control means for controlling the transmission of the signal to the output circuit of the receiving circuit in accordance with the output of the AND gate circuit, whereby the normal operation of the receiving circuit can be ensured even when the signal frequencies arrive with a large arriving time difference and the operation start time is quickened.
Inventors
- 👤 Goro Kusano
- 👤 Hiroshi Kosugi
- 👤 Yasuhiro Yamamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:38
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/453
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
217 words
A multi-frequency signal receiving circuit having an input signal amplifier, a plurality of frequency detectors each including a tuning circuit for generating an output in response to a signal of selected frequency received from the output of the input signal amplifier, and output circuit means connected to the outputs of said frequency detectors for controlling the transmission of the received signal, which comprises: check circuit means connected to said frequency detectors for detecting the existence of a predetermined number of outputs of said frequency detectors and for generating an output only when a predetermined number of outputs are detected; first timing circuit means connected to the output of said check circuit means for delaying the transmission of the output thereof; rectifying circuit means connected to the output of said input signal amplifier for cnverting the received signal energy to a direct-current signal; second timing circuit means connected to the output of said rectifying circuit means for delaying the transmission of the output thereof; first AND gate means connected to said first and second timing circuits and operating when simultaneously receiving the outputs of said first and second timing circuit means; and control means operating in response to the output of said AND gate means for controlling the transmission of the received signal in said output circuit means.
Claim 2
Dependent Claim
217 words
A multi-frequency signal receiving circuit having an input signal amplifier, a plurality of frequency detectors each including a tuning circuit for generating an output in response to a signal of selected frequency received from the output of the input signal amplifier, and output circuit means connected to the outputs of said frequency detectors for controlling the transmission of the received signal, which comprises: check circuit means connected to said frequency detectors for detecting the existence of a predetermined number of outputs of said frequency detectors and for generating an output only when a predetermined number of outputs are detected; first timing circuit means connected to the output of said check circuit means for delaying the transmission of the output thereof; rectifying circuit means connected to the output of said input signal amplifier for cnverting the received signal energy to a direct-current signal; second timing circuit means connected to the output of said rectifying circuit means for delaying the transmission of the output thereof; first AND gate means connected to said first and second timing circuits and operating when simultaneously receiving the outputs of said first and second timing circuit means; and control means operating in response to the output of said AND gate means for controlling the transmission of the received signal in said output circuit means.
Claim 3
Dependent Claim
43 words
A multi-frequency signal receiving circuit according to claim 1, wherein said rectifying circuit is a limiter rectifying circuit which possesses the characteristic of both quick rise and late fall times, said rise and fall times being unchanged according to the input signal level.
Claim 4
Dependent Claim
212 words
A multi-frequency signal receiving circuit according to claim 2, wherein said control means includes a flip-flop circuit which is set by the output of said AND gate means and which is reset by the output of said limiter rectifying circuit, second AND gate means having a pair of inputs connected to the reset output of said flip-flop circuit and the output of said limiter rectifying circuit, respectively, a third timing circuit means connected to the output of said second AND gate means for providing an output with a time delay with respect to the setting of said flip-flop circuit, and means connecting the set output of said flip-flop circuit and the output of said third timing circuit means to said output circuit means whereby the output of each tuning circuit is connected to the output circuit means during a period of time between the appearance of the set side output of said flip-flop circuit and the disappearance of the output of said third timing circuit means and whereby said output circuit means is operated in response to any one of the signal frequencies during said period of time, while the output of any one of said tuning circuits is blocked after the disappearance of the output of said third timing circuit means.
Claim 5
Dependent Claim
57 words
A multi-frequency signal receiving circuit according to claim 3, wherein said output circuit means includes a plurality of self-latching gate circuits each connected between a respective one of said frequency detectors and a respective output of the signal receiving circuit, the output of said flip-flop circuit being connected in control of each of said self-latching gate circuits.
Claim 6
Dependent Claim
49 words
A multi-frequency signal receiving circuit according to claim 4, wherein said output circuit means further includes third AND gate means connected between the outputs of said frequency detectors and said self-latching gate circuits, said third AND gate means being controlled by the output of said third timing circuit means.
Claim 7
Dependent Claim
48 words
A multi-frequency signal receiving circuit according to claim 5, wherein said first AND gate means is connected to the set input of said flip-flip circuit, and further including an inverter circuit connected between the output of said limiter rectifying circuit and the reset input of said flip-flop circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-19 | 1979-07-21 | 1980-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-19 | 1983-07-21 | 1984-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-19 | 1987-07-21 | 1988-01-20 | $7700.00 | Window Closed / Lapsed |