US3930253A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for converting an analog input signal voltage into a digital representation
Assignee: Nikon Corp
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Filing: 1974-01-24
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Granted: 1975-12-30
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Expires: 1994-01-24
Abstract
Abstract A circuit which can convert an analog input signal voltage into a digital representation. The invention provides a plurality of voltage detecting circuit stages which are arranged so that they are not simultaneously brought in conductive to maintain the input impedance at a desired level. Luminous diodes are well arranged to be lighted properly.
Inventors
- 👤 Osamu Maida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:09
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/36; H03M1/361
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
136 words
A circuit for converting an analog input signal from an analog signal source to a digital representation comprising a plurality of electrically sequential switching means (T3, R10, R11, T4, T5; T8, R21, R22, T9, T10; T13, R32, R33, T14, T15) which have different detecting voltages, each of said switching means generating a detecting signal when an analog input signal voltage from said analog signal source equals a detecting voltage, a plurality of electrically sequential operating means (T6, D2; T11, D4; T16, D6; T7, T12, T17) for preventing an analog input current from said analog source from flowing into said plurality of switching means, each of said plurality of operating means being actuated upon application of a detecting signal from the sequentially preceding switching means and the thus actuated operating means actuating the following sequentially operating means.
Claim 2
Dependent Claim
136 words
A circuit for converting an analog input signal from an analog signal source to a digital representation comprising a plurality of electrically sequential switching means (T3, R10, R11, T4, T5; T8, R21, R22, T9, T10; T13, R32, R33, T14, T15) which have different detecting voltages, each of said switching means generating a detecting signal when an analog input signal voltage from said analog signal source equals a detecting voltage, a plurality of electrically sequential operating means (T6, D2; T11, D4; T16, D6; T7, T12, T17) for preventing an analog input current from said analog source from flowing into said plurality of switching means, each of said plurality of operating means being actuated upon application of a detecting signal from the sequentially preceding switching means and the thus actuated operating means actuating the following sequentially operating means.
Claim 3
Dependent Claim
21 words
Circuit according to claim 1, further comprising a plurality of indicating means, which are energized respectively by the sequential switching means.
Claim 4
Dependent Claim
93 words
Circuit according to claim 1, wherein each of said plurality of operating means includes a first control means (T6, D2; T11, D4; T16, D6), a second control means (T7, T12, T17) which is connected to said first control means, generating a control signal and applying the control signal to the following operating means, said first control means being actuated upon application of either the detecting signal from the preceding switching means or the control signal from the preceding second control means and said first control means making inoperative the switching means corresponding thereto.
Claim 5
Dependent Claim
66 words
Circuit according to claim 3, wherein each of said plurality of switching means includes a voltage generating circuit (R10, R11; R21, R22; R32, R33) for generating a predetermined reference voltage and a circuit for comparing the analog input signal voltage to the predetermined reference voltage, the comparing circuit generating a detecting signal when said analog input signal voltage and said reference voltage achieve a predetermined relationship.
Claim 6
Dependent Claim
53 words
Circuit according to claim 4, wherein said comparing circuit includes a voltage detecting transistor to the base of which the analog input signal voltage is applied and to the emitter of which said predetermined reference voltage is applied, said voltage detecting transistor being conductive when the analog input signal reaches said reference voltage.
Claim 7
Dependent Claim
34 words
Circuit according to claim 5, wherein said first control means includes counter-bias transistor means (T6, T11, T16) which makes non-conductive the voltage detecting transistor of the comparing circuit electrically following the first control means.
Claim 8
Dependent Claim
43 words
Circuit according to claim 6, wherein said second control means includes counter-bias detecting transistor means (T7, T12, T17) which detects energization of said counter-bias transistor means and actuates the counter-bias transistor means in the first control circuit electrically following said second control means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-29 | 1979-06-30 | 1979-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-29 | 1983-06-30 | 1983-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-29 | 1987-06-30 | 1987-12-30 | $7700.00 | Window Closed / Lapsed |