US3929512A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor devices
Assignee: US Philips Corp
•
Filing: 1973-09-10
•
Granted: 1975-12-30
•
Expires: 1993-09-10
Abstract
Abstract A method of improving the voltage linearity of a semiconductor resistor for use, for example, in integrated circuit manufacture, which linearity is deteriorated by the loss of carriers in the resistor at the vicinity of a junction separating the resistor region from the semiconductor body. The method consists of bombarding the semiconductor to implant therein in the vicinity of the junction neutral ions, such as neon, forming lattice damage. The concentration of implanted ions and lattice damage is so high as to reduce the effective mobility of charge carriers in the region resulting in the improved voltage linearity.
Inventors
- 👤 Keith Harlow Nicholas
- 👤 Ronald Alfred Ford
- 👤 Julian Robert Anthony Beale
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:52
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/43; H10P; H10P95/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
201 words
A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A REGION OF ONE TYPE CONDUCTIVITY IN A SEMICONDUCTOR BODY PORTION OF THE OPPOSITE TYPE CONDUCTIVITY AND FORMING A JUNCTION WITH THE SEMICONDUCTOR BODY PORTION, SAID ONE TYPE REGION HAVING A HIGH SHEET RESISTANCE AND CONSTITUTING THE RESISTANCE REGIONOF A RESISTOR OF THE SEMICONDUCTOR DEVICE, SAID DEVICE BEING PROCESSED BY STEPS INCLUDING EFFECTING SPACED CONTACTS TO THE RESISTANCE REGION WHEREBY WHEN A VOLTAGE IS APPLIED TO THE CONTACTS THE RESISTOR EXHIBITS A VOLTAGE LINEARITY DETERMINED BY ITS MEASURED RESISTANCE AS A FUNCTION OF APPLIED VOLTAGE, SAID PROCESSING ALSO COMPRISING THE STEP OF BOMBARDING SAID SEMICONDUCTOR BODY PORTION WITH NEUTRAL OR IS FORMED A HIGH CONCENTRATION OF NEUTRAL IONS AND ASSOCIATED SEMICONDUCTOR CRYSTAL LATTICE DAMAGE, THE CONCENTRATION OF IMPLANTED NEUTRAL IONS AND ASSOCIATED SEMICONDUCTOR CRYSTAL LATTICE DAMAGE IN THE RESISTANCE REGION OF THE FINISHED DEVICE AFTER THE PROCESSING, AT LEAST INE THE VINCINITY OF THE SAID JUCTION, BEING SO HIGH THAT THE EFFECTIVE MOBILITY OF MAJORITY CHARGE CARRIERS IN THE RESISTANCE REGION IN THE VICINITY OF THE SAID JUNCTION IS AT MOST ONE-THIRD OF THE VALUE IN THE ABSENCE OF THE IMPLANTED NEUTRAL IONS AND ASSOCIATED DAMAGE WHEREBY THE RESISTOR EXHIBITS IMPROVED VOLTAGE LINARITY.
Claim 2
Independent Claim
201 words
A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A REGION OF ONE TYPE CONDUCTIVITY IN A SEMICONDUCTOR BODY PORTION OF THE OPPOSITE TYPE CONDUCTIVITY AND FORMING A JUNCTION WITH THE SEMICONDUCTOR BODY PORTION, SAID ONE TYPE REGION HAVING A HIGH SHEET RESISTANCE AND CONSTITUTING THE RESISTANCE REGIONOF A RESISTOR OF THE SEMICONDUCTOR DEVICE, SAID DEVICE BEING PROCESSED BY STEPS INCLUDING EFFECTING SPACED CONTACTS TO THE RESISTANCE REGION WHEREBY WHEN A VOLTAGE IS APPLIED TO THE CONTACTS THE RESISTOR EXHIBITS A VOLTAGE LINEARITY DETERMINED BY ITS MEASURED RESISTANCE AS A FUNCTION OF APPLIED VOLTAGE, SAID PROCESSING ALSO COMPRISING THE STEP OF BOMBARDING SAID SEMICONDUCTOR BODY PORTION WITH NEUTRAL OR IS FORMED A HIGH CONCENTRATION OF NEUTRAL IONS AND ASSOCIATED SEMICONDUCTOR CRYSTAL LATTICE DAMAGE, THE CONCENTRATION OF IMPLANTED NEUTRAL IONS AND ASSOCIATED SEMICONDUCTOR CRYSTAL LATTICE DAMAGE IN THE RESISTANCE REGION OF THE FINISHED DEVICE AFTER THE PROCESSING, AT LEAST INE THE VINCINITY OF THE SAID JUCTION, BEING SO HIGH THAT THE EFFECTIVE MOBILITY OF MAJORITY CHARGE CARRIERS IN THE RESISTANCE REGION IN THE VICINITY OF THE SAID JUNCTION IS AT MOST ONE-THIRD OF THE VALUE IN THE ABSENCE OF THE IMPLANTED NEUTRAL IONS AND ASSOCIATED DAMAGE WHEREBY THE RESISTOR EXHIBITS IMPROVED VOLTAGE LINARITY.
Claim 3
Dependent Claim
34 words
A method as claimed in claim 1, wherein the said effective mobility is at least one order of magnitude less than the value in the absence of the implanted neutral ions and associated damage.
Claim 4
Dependent Claim
20 words
A method as claimed in claim 2, wherein the implanted neutral ion dose is at least 2 X 1013 ions/cm2.
Claim 5
Dependent Claim
12 words
A method as claimed in claim 3, wherein the ions are neon.
Claim 6
Dependent Claim
27 words
A method as claimed in claim 3, wherein the conductivity type of the resistance region is determined by implanting impurity ions characteristic of the one type conductivity.
Claim 7
Dependent Claim
20 words
A method as claimed in claim 1, wherein the resistor has a sheet resistance of at least 20 K. ohms/square.
Claim 8
Dependent Claim
16 words
A method as claimed in claim 6, wherein said sheet resistance is at least 50 K.ohms/square.
Claim 9
Dependent Claim
25 words
A method as claimed in claim 1, wherein subsequent to the neutral ion implantation, the body is heated at a temperature of at most 500*C.
Claim 10
Dependent Claim
29 words
A method as claimed in claim 1, wherein the neutral ions are implanted throughout the part of the body where the resistance region is to be or is formed.
Claim 11
Dependent Claim
40 words
A method as claimed in claim 1, wherein the energy of the bombarding neutral ions is such that the neutral ions are implanted to form a peak concentration immediately below where the said junction is to be or is formed.
Claim 12
Independent Claim
193 words
A method of manufacturing a semiconductor device having a region of one type conductivity in a semiconductor body portion of the opposite type conductivity and forming a junction with the semiconductor body portion, said one type region having a high sheet resistance and constituting the resistance region of a resistor of the semiconductor device, said device being processed by steps including effecting spaced contacts to the resistance region whereby when a voltage is applied to the contacts the resistor exhibits a voltage linearity determined by its measured resistance as a function of applied voltage, said processing also comprising the step of bombarding said semiconductor body portion with neutral ions to implant in the body at least where the junction is to be or is formed a high concentration of neutral ions and associated semiconductor crystal lattice damage, the concentration of implanted neutral ions and associated semiconductor crystal lattice damage in the resistance region of the finished device, at least in the vicinity of the said junction, being so high that the temperature coefficient of the resistor has a highly negative value of the order of 103ppm/*C whereby the resistor exhibits improved voltage linearity.
Claim 13
Independent Claim
193 words
A method of manufacturing a semiconductor device having a region of one type conductivity in a semiconductor body portion of the opposite type conductivity and forming a junction with the semiconductor body portion, said one type region having a high sheet resistance and constituting the resistance region of a resistor of the semiconductor device, said device being processed by steps including effecting spaced contacts to the resistance region whereby when a voltage is applied to the contacts the resistor exhibits a voltage linearity determined by its measured resistance as a function of applied voltage, said processing also comprising the step of bombarding said semiconductor body portion with neutral ions to implant in the body at least where the junction is to be or is formed a high concentration of neutral ions and associated semiconductor crystal lattice damage, the concentration of implanted neutral ions and associated semiconductor crystal lattice damage in the resistance region of the finished device, at least in the vicinity of the said junction, being so high that the temperature coefficient of the resistor has a highly negative value of the order of 103ppm/*C whereby the resistor exhibits improved voltage linearity.
Claim 14
Dependent Claim
25 words
A method as claimed in claim 5 wherein the neutral ion implantation is effected before the implantation or impurity ions characteristic of the one-type conductivity.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-29 | 1979-06-30 | 1979-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-29 | 1983-06-30 | 1983-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-29 | 1987-06-30 | 1987-12-30 | $7700.00 | Window Closed / Lapsed |