Programmable bit clock oscillator for controlling the processing of binary digits

Claim 2

A programmable oscillator for controlling the processing of binary digits, comprising: oscillator means for providing an output clock signal indicative of the operating speed of said oscillator means, counter means for receiving binary data indicative of the desired operating speed of said oscillator means, said counter means being responsive both to the output clock signal from said oscillator means and to synchronizing signals which control the countdown of said counter means from the binary data value for providing an output signal, comparator means for comparing the output of said counter means with synchronizing signals, correction means responsive to the output of said comparator means for generating incremental correction signals which control the operating speed of said oscillator means, and timing means responsive to one of said synchronizing signals for generating a disabling signal which further controls said oscillator means such that said oscillator means commences predetermined bit streams with the same phase.

Claim 3

The oscillator as defined in claim 1 in which said oscillator means comprises a second comparator means and a voltage controlled diode whose anode is connected to the inverting input terminal of said second comparator means, the noninverting input of said second comparator means being connected to a reference potential, and in which said incremental correction signals are applied through said diode to the inverting input of said second comparator means.

Claim 4

The oscillator as defined in claim 2 in which the output voltage of said second comparator means is fed back through a load to the inverting input for providing an oscillating signal at the output of said second comparator means and fed back through a load divider means to the noninverting input terminal to implement hysteresis to said oscillator means.

Claim 5

The oscillator as defined in claim 3 in which said disabling signal is applied as well to the noninverting input terminal of said second comparator means for synchronously starting and stopping the output clock signal of said oscillator means.

Claim 6

A programmable oscillator for controlling the processing of binary digits for display on a scan line device, comprising: oscillator means for providing an output clock signal for synchronous control of a bit stream which is used to construct characters for display on said device, counter means for receiving binary bits indicative of the number of bits per scan line desired, said counter means being responsive both to the output clock signal from said oscillator means and to synchronizing signals which control the countdown of said counter means from the value of the binary bits for providing an output signal, comparator means for comparing the output of said counter means with synchronizing signals, correction means responsive to the output of said comparator means for generating incremental correction signals every scan line to control the speed of said oscillator means whereby the number of bits per scan line is controlled, and timing mEans responsive to one of said synchronizing signals for generating a disabling signal which further controls said oscillator means such that said oscillator means commences each scan line with the same phase.

Claim 7

A programmable oscillator for controlling the processing of binary digits for display on a scan line device, comprising: oscillator means for providing an output clock signal for synchronous control of a bit stream which is used to construct characters for display on said device, counter means for receiving binary bits indicative of the number of bits per scan line desired, said counter means being responsive both to the output clock signal from said oscillator means and to synchronizing signals which control the countdown of said counter means from the value of the binary bits for providing an output signal, comparator means for comparing the output of said counter means with synchronizing signals, correction means responsive to the output of said comparator means for generating incremental correction signals every scan line to control the speed of said oscillator means whereby the number of bits per scan line is controlled, and timing mEans responsive to one of said synchronizing signals for generating a disabling signal which further controls said oscillator means such that said oscillator means commences each scan line with the same phase.

Claim 8

The oscillator as defined in claim 5 in which said oscillator means comprises a second comparator means and a voltage controlled diode whose anode is connected to the inverting input terminal of said second comparator means, the noninverting input of said second comparator means being connected to a reference potential, and in which said incremental correction signals are applied through said diode to the inverting input of said second comparator means.

Claim 9

The oscillator as defined in claim 6 in which the output voltage of said second comparator means is fed back through a load to the inverting input for providing an oscillating signal at the output of said second comparator means and fed back through a load divider means to the noninverting input terminal to implement hysteresis to said oscillator means.

Claim 10

The oscillator as defined in claim 7 in which said disabling signal is applied as well to the noninverting input terminal of said second comparator means for synchronously starting and stopping the output clock signal of said oscillator means.