US3924110A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Calculator system featuring a subroutine register
Assignee: Texas Instruments Inc
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Filing: 1973-09-13
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Granted: 1975-12-02
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Expires: 1993-09-13
Abstract
Abstract Disclosed is a portable electronic calculator system implemented in LSI semiconductor technology which features subroutine storage. The subroutine storage is combined with keyboard and flag storage and is preferably implemented as a sequentially addressed memory. The system includes a permanent store memory for storing instruction words, which is addressable by the keyboard storage. After addressing the memory according to a location specified in the keyboard storage, an exchange is executed between the keyboard storage and subroutine. Subsequently, another exchange is executed effecting return of the operating program to the location in the memory previously specified. The subroutine register is under control of the instruction memory, and functions only to exchange its contents with that of the keyboard storage.
Inventors
- 👤 Michael J Cochran
- 👤 Jr Charles P Grant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:00
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/445; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
192 words
In an electronic calculator system implemented on at least one semiconductor chip, having a clock system for providing cycle and sub-cycle timing, instruction memory means for storing instructions, address register means for addressing the instruction memory means, and input means for receiving external commands, ultimately as addresses of the instruction memory means, the improvement comprising: a. keyboard storage means, operatively connected to the input means for storing multi-bit instruction memory addresses and selectively connected to the address register means for transmitting the memory addresses; b. sub-routine storage means, selectively connectable only to the keyboard storage means, for receiving and storing memory addresses, and for selectively transmitting memory addresses back to the keyboard storage means; and c. control means, operatively connected to the address register means, the keyboard storage means, the sub-routine storage means, and to the instruction memory means, responsive to a selected instruction word from the instruction memory means for causing the transfer of the contents of the keyboard storage means to the address register means and to the subroutine storage means and, under the control of a selected instruction word, from the sub-routine storage means to the keyboard storage means.
Claim 2
Dependent Claim
192 words
In an electronic calculator system implemented on at least one semiconductor chip, having a clock system for providing cycle and sub-cycle timing, instruction memory means for storing instructions, address register means for addressing the instruction memory means, and input means for receiving external commands, ultimately as addresses of the instruction memory means, the improvement comprising: a. keyboard storage means, operatively connected to the input means for storing multi-bit instruction memory addresses and selectively connected to the address register means for transmitting the memory addresses; b. sub-routine storage means, selectively connectable only to the keyboard storage means, for receiving and storing memory addresses, and for selectively transmitting memory addresses back to the keyboard storage means; and c. control means, operatively connected to the address register means, the keyboard storage means, the sub-routine storage means, and to the instruction memory means, responsive to a selected instruction word from the instruction memory means for causing the transfer of the contents of the keyboard storage means to the address register means and to the subroutine storage means and, under the control of a selected instruction word, from the sub-routine storage means to the keyboard storage means.
Claim 3
Dependent Claim
24 words
The calculator system of claim 1 further comprising strobing means, responsive to the clock system for providing a strobe pulse at each sub-cycle time.
Claim 4
Dependent Claim
31 words
The calculator system of claim 2 wherein the keyboard storage means and the sub-routine storage means each coMprise a sequentially addressed memory having digit columns strobed sequentially by the strobe pulse.
Claim 5
Dependent Claim
29 words
The calculator system of claim 3 wherein the sequentially addressed memory has separate input and output lines and has common read/write address lines sequentially strobed by the strobe pulse.
Claim 6
Dependent Claim
167 words
In an electronic calculator system of the type implemented in LSI circuit technology and having an instruction read-only-memory for storing a relatively large number of instruction words and which is addressable through means responsive to programmable storage means, the programmable storage means comprising address register means for addressing the memory and first storage means for storing and communicating externally and internally a multi-bit word, and a sub-routine storage means under control of the instruction read-only-memory for selectively receiving only the word from the first storage means and for selectively re-transferring the word only to the first storage means, the method of addressing the instruction read-only-memory comprising the steps of: a. entering a binary word in the first storage means representing a specific address of the instruction read-only-memory; b. transmitting the representation to the address register means; c. transferring the representation to the sub-routine storage means; d. addressing the instruction read-only-memory with the representation; and e. re-transferring the representation in the sub-routine storage to the first storage means.
Claim 7
Dependent Claim
167 words
In an electronic calculator system of the type implemented in LSI circuit technology and having an instruction read-only-memory for storing a relatively large number of instruction words and which is addressable through means responsive to programmable storage means, the programmable storage means comprising address register means for addressing the memory and first storage means for storing and communicating externally and internally a multi-bit word, and a sub-routine storage means under control of the instruction read-only-memory for selectively receiving only the word from the first storage means and for selectively re-transferring the word only to the first storage means, the method of addressing the instruction read-only-memory comprising the steps of: a. entering a binary word in the first storage means representing a specific address of the instruction read-only-memory; b. transmitting the representation to the address register means; c. transferring the representation to the sub-routine storage means; d. addressing the instruction read-only-memory with the representation; and e. re-transferring the representation in the sub-routine storage to the first storage means.
Claim 8
Dependent Claim
43 words
The method of addressing an instruction read-only-memory of claim 5, further including, subsequent to the step of re-transferring, the step of sending the representation to the instruction read-only-memory for relocating the operational sequence of the calculator back to the specific instruction read-only-memory location.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-01 | 1979-06-02 | 1979-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-01 | 1983-06-02 | 1983-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-01 | 1987-06-02 | 1987-12-02 | $7700.00 | Window Closed / Lapsed |