US3924082A
Expired / Lapsed
US
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Conference circuits for use in telecommunications systems
Assignee: GPT INTERNATIONAL Ltd
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Filing: 1974-02-04
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Granted: 1975-12-02
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Expires: 1994-02-04
Abstract
Abstract A conference circuit for use in a PCM system. ''n'' channels requiring conference are arranged serially in n-channel frames. Each frame of n channels is sampled by transfer to an n-stage cyclic shift register and circulated through the register once. n-1 of the shift register stages are permanently added to give every possible combination of n-1 of the n channels in a frame as the n channels circulate through the register. Each such combination of n-1 channels is then clearly the conference signal required by the remaining channel subscriber. The various combinations of n-1 channels are then simply distributed to the appropriate ''remaining'' channel subscribers.
Inventors
- 👤 Stephen Edward Oliver
- 👤 Nicholas Richard Winch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:04
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/42; H04M3/56; H04M3/561
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
218 words
A conference circuit for use in a telecommunication system, said circuit comprising: a cyclic shift register having more than two stages each of which stages can hold a digital data word; means for clocking said shift register at a predetermined clock rate; means for writing digital data words from more than two input channels into respective stages of said shift register, at one point in each cycle of said register; digital adding means coupled to all but one of said stages of said register, for adding together the contents of the stages coupled thereto so as to produce a digital output word each time the shift register is clocked, said digital output word thus being a conference word for transmission to a conferee associated with the data word temporarily occupying said one of said stages at the particular said time, which data word was not included in the adding process at the particular said time; and a plurality of output channels for respective conferees, and corresponding to the successive states of said shift register in a said cycle, each said output channel receiving a respective said digital output word in the corresponding state of said shift register, whereby each output channel receives the sum of the data words from all but a corresponding one of the input channels.
Claim 2
Dependent Claim
218 words
A conference circuit for use in a telecommunication system, said circuit comprising: a cyclic shift register having more than two stages each of which stages can hold a digital data word; means for clocking said shift register at a predetermined clock rate; means for writing digital data words from more than two input channels into respective stages of said shift register, at one point in each cycle of said register; digital adding means coupled to all but one of said stages of said register, for adding together the contents of the stages coupled thereto so as to produce a digital output word each time the shift register is clocked, said digital output word thus being a conference word for transmission to a conferee associated with the data word temporarily occupying said one of said stages at the particular said time, which data word was not included in the adding process at the particular said time; and a plurality of output channels for respective conferees, and corresponding to the successive states of said shift register in a said cycle, each said output channel receiving a respective said digital output word in the corresponding state of said shift register, whereby each output channel receives the sum of the data words from all but a corresponding one of the input channels.
Claim 3
Dependent Claim
133 words
A conference circuit according to claim 1, for use in a telecommunication system in which said input channels are time-division multiplexed together, and wherein said means for writing digital data words into said cyclic shift register comprises: a linear shift register having more than two stages each of which stages can hold a digital data word; means for clocking said linear shift register in synchronism with the multiplexing rate of said input channels, so as to cause successive data words appearing on said input channels to be read respectively into successive stages of said linear shift register; and means for transferring the contents of at least some of the stages of said linear shift register into respective stages of said cyclic shift register, at one point in each cycle of the latter register.
Claim 4
Dependent Claim
63 words
A conference circuit according to claim 1, wherein said cyclic shift register comprises two sections and the circuit includes means for short circuiting one of said two sections so as to permit the contents of the other section to circulate within that other section alone, and means for connecting said adding means to all but one of the stages of said other section.
Claim 5
Dependent Claim
97 words
A conference circuit according to claim 1, wherein each output word from said adding means comprises n bits in 2n 1 complement form, n being greater than the number, m, of bits in each input word entered into said cyclic register, the conference circuit including out-of-limit detection means for producing an out-of-limit signal with respect to each said output word which lies outside the range 2n 1 + or - (2m-1), and means responsive to said out-of-limit signal for applying the maximum possible magnitude bits to the output channel in place of such an out-of-limit output word.
Claim 6
Dependent Claim
213 words
A conference circuit according to claim 1, wherein each output word from said adding means comprises n bits in 2n 1 complement form, n being greater than the number, m, of bits in each input word entered into said cyclic register, the conference circuit including a decomplementation circuit connected to receive n-bit output words from said adding means in 2n 1 complement form, and to convert each such word into an (m + 1) bit word consisting of a sign bit plus m magnitude bits, the decomplementation circuit comprising: an m-bit adder having two m-bit inputs and an (m + 1) bit output; means for applying the m least significant bits of each n-bit output word to one m-bit input of the adder, without change if the most significant bit of the n-bit output word is 1 and with each bit inverted if the most significant bit of the n-bit output word is 0, and means for applying the inverse of the most-significant bit of the n-bit output word to the least significant bit of the other m-bit input of said adder, so as to cause unity to be added to the m bits applied to the first-mentioned input of the adder if the most-significant bit of the n-bit output word is 0.
Claim 7
Dependent Claim
99 words
A conference circuit according to claim 5, wherein said out-of-limit detection means comprises logic gating means for producing said out-of-limit signal in the event that either: i. the most significant bit of said n-bit output word is 1 and any one or more of the (n-m-1) next most significant bits is equal to 1; or ii. the most significant bit of said n-bit output word is 0 and at least one of the (n-m-1) next most significant bits is equal to 0, or iii. the most significant bit of the output of the m-bit adder is equal to 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-01 | 1979-06-02 | 1979-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-01 | 1983-06-02 | 1983-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-01 | 1987-06-02 | 1987-12-02 | $7700.00 | Window Closed / Lapsed |