Integrated IGFET bucket-brigade circuit

Claim 1

An integrated bucket-brigade circuit wherein there is provided a plurality of stages each containing a transistor and a capacitor coupled between the gate and drain electrode thereof, and coupled together such that the drain electrode of each transistor is connected to the source electrode of the next successive transistor, and wherein a first clock signal is coupled to the gate terminals of even-numbered transistors and the complement of said first square wave clock signal controls the gate terminals of the odd-numbered transistors, comprising: a source of operating voltage; first and second sources of clock pulses, said first source coupled to said even-numbered transistors and said second source coupled to said odd-numbered transistors; and a row of field-effect transistors of the depletion-layer type having source and drain regions, said field-effect transistors employing gate electrodes on an insulated-gate layer, wherein the last transistor in said row is provided with an electrical terminal to which said source of operating voltage is coupled, said operating voltage having polarity opposite to the polarity of said clock pulses and having magnitude greater than the pinch-off voltage of said last transistor.