Digital comparator with multiple references

Claim 1

Series-parallel electronic comparator comprising units for comparing equal-order digits of an input discrete value with reference discrete values, each unit having inputs being fed with similar digits of the input discrete value and the reference discrete values; a digit transfer bus for said input discrete value; digit transfer buses for said reference discrete values; NOT-circuits in each said unit for comparing equal-order digits, the input of the first NOT-circuit being connected to said digit transfer bus of the input discrete value, and the input of each of the remaining NOT-circuits being connected to each said digit transfer bus of a respective reference discrete value; a first group of AND-circuits in each said unit for comparing equal-order digits, each AND-circuit having a first and a second input and an output; a second group of AND-circuits in each said unit for comparing equal-order digits, each AND-circuit having a first and a second input and an output; said AND-circuits in said first group having the first inputs thereof connected to the outputs of respective of said remaining NOT-circuits, said second inputs thereof being combined and connected to said digit transfer bus of the input discrete value, said AND-circuits in said second group having the first inputs thereof connected to said digit transfer buses for transferring the digits of respective reference discrete values and the second inputs thereof being combined and connected to the output of said first NOT-circuit, the input thereof being connected to said digit transfer bus of the input discrete value; a first group of OR-circuits for transferring the comparison result when said digit of said input discrete value is represented by a logic 1 and said digit of said reference discrete value, by a logic 0; a second group of ORcircuits transferring the comparison result when said digit of said input discrete value is represented by a logic 0, said digit of said reference discrete value, by a logic 1; said OR-circuits in said first group having their inputs connected to said outputs of said AND-circuits in said first group; said OR-circuits in said second group having their inputs connected to said outputs of said AND-circuits in said second group; memory elements for storing comparison results, each having writing, reading and inhibit inputs, and inhibit inputs being connected to the outputs of respective of said OR-circuits in the first group, and the writing inputs being connected to the outputs of respective of said OR-circuits in the second group; a decoder for generating an output signal according to comparison results, said decoder comprising a group of inhibit AND-circuits, each having first and second writing inputs, first and second reading inputs, an inhibit input and an output, a group of OR-circuits, each having two inputs and an output, said inputs of said inhibit ANDcircuits and said inputs of said OR-circuits of said decoder being coupled to said outputs of said memory elements so that said output of each of said memory elements is connected directly to said first writing input of said respective inhibit ANDcircuit and through said series-connected OR-circuits to said inhibit inputs of all succeeding of said inhibit AND-circuits of said decoder; a plurality of control buses for receiving synchronizing clock pulses, some of said control buses being coupled to said respective units for comparing equal-order digits, each said bus being coupled to each sAid unit for respectively comparing equal-order digits, one of said control buses further being connected to said reading inputs of all of said memory elements, and the remaining of said control buses being respectively connected to said combined first and second reading inputs and to said combined second writing inputs of all of said inhibit AND-circuits in said decoder for generating an output signal according to comparison results; and a clock-pulse generator for synchronizing operation of said series-parallel electronic comparator, said clock-pulse generator including one starting input and a plurality of outputs, each being connected to one of said control buses respectively.