Pulse summing circuit

Claim 2

A circuit arrangement for totalizing the pulses selected by a plurality Of selecting devices from the output of a common pulse generator in which each selecting device controls the percentage of a particular component being blended with other components in an automatic blending system and comprising a common pulse generator, a plurality of selecting devices coupled to said common pulse generator for controlling the percentages of particular components being blended, each of which selects and passes a percentage of the pulses generated by said common pulse generator, a plurality of gates equal in number to the number of selecting devices, means connecting the selecting device outputs separately and individually to said gates, means for producing a train of gating pulses having a high repetition rate as compared to the pulse repetition rate of said generator, means for applying said gating pulses sequentially to individual ones of said gates, thereby to sequentially open the same, and a common output circuit coupled to said gates.

Claim 3

Arrangement according to claim 1, including also counter means connected to said common output circuit.

Claim 4

Arrangement of claim 1, wherein each of said gates is a NAND gate to one input of which the output of a corresponding selecting device is connected and to the other input of which a gating pulse is applied.

Claim 5

Arrangement of claim 1, wherein said applying means comprises a decoder supplied with said gating pulses, and means connecting the individual gates to respective output terminals of said decoder.

Claim 6

Arrangement set forth in claim 4, wherein said decoder operates, upon the completion of each sequence of application of gating pulses to the gates, to cut off the supply of gating pulses to such decoder.

Claim 7

Arrangement described in claim 4, including also counter means connected to said common output circuit.

Claim 8

Arrangement set forth in claim 4, wherein each of said gates is a NAND gate to one input of which the output of a corresponding selecting device is connected and the other input of which is connected to a corresponding output terminal of the decoder.

Claim 9

A circuit arrangement for totalizing the pulses selected by a plurality of selecting devices from the output of a common pulse generator in which each selecting device controls the percentage of a particular component being blended with other components in an automatic blending system and comprising a common pulse generator, a plurality of selecting devices coupled to said common pulse generator for controlling the percentages of particular components being blended, each of which selects and passes a percentage of the pulses generated by said common pulse generator, a plurality of gates equal in number to the number of selecting devices, means connecting the selecting device outputs separately and individually to said gates, a source of square waves having a frequency high as compared to the frequency of said generator, a BCD counter, a decoder driven by the output of said counter, means for feeding square waves from said source to said counter, means for developing strobing pulses from said square waves, means for utilizing the last-mentioned pulses to strobe said decoder, means connecting the individual gates to respective output terminals of said decoder, and a common output circuit coupled to said gates.

Claim 10

A circuit arrangement for totalizing the pulses selected by a plurality of selecting devices from the output of a common pulse generator in which each selecting device controls the percentage of a particular component being blended with other components in an automatic blending system and comprising a common pulse generator, a plurality of selecting devices coupled to said common pulse generator for controlling the percentages of particular components being blended, each of which selects and passes a percentage of the pulses generated by said common pulse generator, a plurality of gates equal in number to the number of selecting devices, means connecting the selecting device outputs separately and individually to said gates, a source of square waves having a frequency high as compared to the frequency of said generator, a BCD counter, a decoder driven by the output of said counter, means for feeding square waves from said source to said counter, means for developing strobing pulses from said square waves, means for utilizing the last-mentioned pulses to strobe said decoder, means connecting the individual gates to respective output terminals of said decoder, and a common output circuit coupled to said gates.

Claim 11

Arrangement according to claim 8, including also counter means connected to said common output circuit.

Claim 12

Arrangement of claim 8, wherein each of said gates is a NAND gate to one input of which the output of a corresponding selecting device is connected and the other input of which is connected to a respective output terminal of said decoder.

Claim 13

Arrangement set forth in claim 8, wherein each pulse developed at the final output terminal of said decoder is utilized to disable the means which feeds square waves to said counter.

Claim 14

Arrangement set forth in claim 8, wherein each pulse developed at the final output terminal of said decoder is utilized to cut off the supply of square waves to the strobinG pulse developing means.

Claim 15

Arrangement set forth in claim 8, wherein each pulse developed at the final output terminal of said decoder is utilized to disable the means which feeds square waves to said counter, and to cut off the supply of square waves to the strobing pulse developing means.

Claim 16

Arrangement of claim 13, wherein each of said gates is a NAND gate to one input of which the output of a corresponding selecting device is connected and the other input of which is connected to a respective output terminal of said decoder.

Claim 17

A circuit as set forth in claim 1 wherein said common output circuit includes a counter means for counting the pulses gated by said plurality of gates during a time interval determined by the generation of a predetermined number of pulses by said common pulse generator, means for storing the output of said counter means at the end of said time interval, and means for updating said storing means after the passage of each succeeding said time interval and including means for resetting said counter means to zero at the end of each of said time interval to allow said counter means to begin a new counting cycle during a new time interval.

Claim 18

A circuit as set forth in claim 8 wherein said common output circuit includes a counter means for counting the pulses gated by said plurality of gates during a time interval determined by the generation of a predetermined number of pulses by said common pulse generator, means for storing the output of said counter means at the end of said time interval, and means for updating said storing means after the passage of each succeeding said time interval and including means for resetting said counter means to zero at the end of each said time interval to allow said counter means to begin a new counting cycle during a new time interval.