US3920919A
Expired / Lapsed
US
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Device for checking a multiplex digital train
Assignee: Alcatel CIT SA
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Filing: 1974-07-02
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Granted: 1975-11-18
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Expires: 1994-07-02
Abstract
Abstract The invention comes within the branch of data transmission comprising the multiplexing of k digital unitary trains of rhythms substantially equal into a single digital train having a rhythm substantially k times faster than the unitary trains and the reverse demultiplexing. It concerns a device enabling the checking of multiplexing/demultiplexing operations by comparison between a word having a determined length sampled in a (slow) unitary train and a word having the same length sampled in the (rapid) multiplexed train.
Inventors
- 👤 Claude Aillet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:05
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
246 words
A device for checking the correspondence between a rapid multiplex digital train and digital non-synchronized rhythm trains about k times slower, said device comprising: memory means for storing a first word of a predetermined number of bits q, said first word sampled on one of k slow input trains Mi having a rhythm Fi of a multiplexer and k slow output trains Ni having a rhythm Gi of a demultiplexer; divider means for dividing by k a rapid rhythm F of a rapid output train M of said multiplexer and a rapid rhythm G of a rapid input train N of said demultiplexer; first register means for providing a second word of said predetermined number of bits q, said second word being sampled on said rapid train at said rapid rhythm; comparison means for comparing said first and second words for coincidence during a predetermined selection time; timing control means for controlling the timing of said rapid rhythm divided by k as a function of a lack of coincidence in said comparison means to achieve coincidence, said timing control means providing a timing regulation mode; error checking means for detecting errors in said coincidence of said first and second words during said predetermined selection time, said error checking means providing an error checking mode; and alarm indicating means for indicating an alarm signal representative of at least one of said error in said coincidence and a failure to achieve a coincidence during said predetermined selection time.
Claim 2
Independent Claim
246 words
A device for checking the correspondence between a rapid multiplex digital train and digital non-synchronized rhythm trains about k times slower, said device comprising: memory means for storing a first word of a predetermined number of bits q, said first word sampled on one of k slow input trains Mi having a rhythm Fi of a multiplexer and k slow output trains Ni having a rhythm Gi of a demultiplexer; divider means for dividing by k a rapid rhythm F of a rapid output train M of said multiplexer and a rapid rhythm G of a rapid input train N of said demultiplexer; first register means for providing a second word of said predetermined number of bits q, said second word being sampled on said rapid train at said rapid rhythm; comparison means for comparing said first and second words for coincidence during a predetermined selection time; timing control means for controlling the timing of said rapid rhythm divided by k as a function of a lack of coincidence in said comparison means to achieve coincidence, said timing control means providing a timing regulation mode; error checking means for detecting errors in said coincidence of said first and second words during said predetermined selection time, said error checking means providing an error checking mode; and alarm indicating means for indicating an alarm signal representative of at least one of said error in said coincidence and a failure to achieve a coincidence during said predetermined selection time.
Claim 3
Dependent Claim
62 words
A device according to claim 1, wherein said timing control means includes a first counter means for receiving a signal from the output of said comparison means and a second counter means for counting repetitive intervals of said predetermined selection time, said first counter means operating as a major detector of said lack of coincidence in connection with said second counter means.
Claim 4
Dependent Claim
56 words
A device according to claim 2, wherein said timing control means further includes switch means for alternatively switching between a first and second operating position respectively providing said timing regulation mode and said error checking mode, said switch means receiving a signal from said first counter means representative of a predetermined number of lack of coincidences.
Claim 5
Dependent Claim
72 words
A device according to claim 3, wherein said timing control means further includes a third counter means for checking the timing of said rapid rhythm divided by k in response to a signal from said second counter means, said third counter means having a greater capacity than said first and second counter means, and said third counter means being reset to zero when said switch means is in said first operating position.
Claim 6
Dependent Claim
54 words
A device according to claim 4, wherein said switch means includes a first flip-flop means for controlling said switch means, said first flip-flop means being set to zero when said third counter means is at full capacity such that said switch means is changed from said first operating position to said second operating position.
Claim 7
Dependent Claim
53 words
A device according to claim 5, wherein error checking means includes a fourth counter means for resetting said first flip-flop means to 1 upon receipt by said fourth counter means of a predetermined lack of coincidence signal when said switch means is in said second operating position to effect a new timing check.
Claim 8
Dependent Claim
31 words
A device according to claim 6, wherein said alarm signal is indicated when said fourth counter means receives a lack of coinCidence signal subsequent to said predetermined lack of coincidence signal.
Claim 9
Dependent Claim
78 words
A device according to claim 7, wherein said first flip-flop means has an output connected to a control input of a second flip-flop means, said second flip-flop means being interrogated by a predetermined pulse emitted at the end of said selection time, and said second flip-flop being reset to zero by a second pulse slightly delayed from said predetermined pulse to actuate said alarm indicating means if said first flip-flop has maintained its state during said selection time.
Claim 10
Dependent Claim
43 words
A device according to claim 1, wherein said error check means includes circuit means for reactivating said timing control means at a first occurring error in said coincidence, and further including means for resuming said error checking mode upon a second occurring error.
Claim 11
Dependent Claim
35 words
A device according to claim 1, wherein said memory means includes a shift register means having q flip-flops, the advance line of said shift register means being blocked after filling of said shift register means.
Claim 12
Dependent Claim
44 words
A device according to claim 9, wherein each of said memory means and said first register means are preceded by delay means, said delay means respectively receiving said slow input train Mi of said multiplexer and said rapid input train N of said demultiplexer.
Claim 13
Dependent Claim
46 words
A device according to claim 11, wherein said slow output train Ni of said demultiplexer is applied to said advance line of said shift register means, and said rapid output train M of said multiplexer is applied to the advance line of said first register means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-17 | 1979-05-19 | 1979-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-17 | 1983-05-19 | 1983-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-17 | 1987-05-19 | 1987-11-18 | $7700.00 | Window Closed / Lapsed |