US3919650A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mark frequency detector circuit
Assignee: MI 2 329102
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Filing: 1973-08-15
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Granted: 1975-11-11
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Expires: 1993-08-15
Abstract
Abstract A mark frequency detector circuit for a data coupler having originate and answer capabilities for communicating with another remote data terminal or digital computer over conventional telephone lines. A mark detector circuit to detect the mark frequency signals from those spurious or ambient noise signals that may pass through the data coupler receive frequency filter sections. The circuit per se utilizes a simple arrangement of a pair of FET switches and a pair of operational amplifiers; providing a voltage comparison to detect the presence or absence of a pure mark frequency signal.
Inventors
- 👤 Richard D Fretwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:19
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/144
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
191 words
A mark frequency detector circuit for a data coupler for detecting mark and space frequency signals comprising: ground means, input means for receiving a positive signal indicative of a mark frequency in the upright mode of operation and a negative signal as a space frequency and a negative signal indicative of a mark frequency in the inverted mode of operation and a positive signal as a space frequency, said signals having a representative value; a first and second switching means receiving said input signals, the first of said switching means operative in response to said positive signal and the second of said switching means operative in response to said negative signal; inverting means having the output of said negative responsive switching means connected thereto and voltage comparison means having the output of said inverting means connected thereto; in upright mode of operation said positive output of said input means is connected to said voltage comparison means and the output of said inverter is shunted to said ground means, reference voltage determining means connected to said voltage comparison means for comparing the output signals from said switching means with a reference voltage.
Claim 2
Dependent Claim
191 words
A mark frequency detector circuit for a data coupler for detecting mark and space frequency signals comprising: ground means, input means for receiving a positive signal indicative of a mark frequency in the upright mode of operation and a negative signal as a space frequency and a negative signal indicative of a mark frequency in the inverted mode of operation and a positive signal as a space frequency, said signals having a representative value; a first and second switching means receiving said input signals, the first of said switching means operative in response to said positive signal and the second of said switching means operative in response to said negative signal; inverting means having the output of said negative responsive switching means connected thereto and voltage comparison means having the output of said inverting means connected thereto; in upright mode of operation said positive output of said input means is connected to said voltage comparison means and the output of said inverter is shunted to said ground means, reference voltage determining means connected to said voltage comparison means for comparing the output signals from said switching means with a reference voltage.
Claim 3
Dependent Claim
31 words
The detector circuit of claim 1 wherein said comparison means is an operational amplifier and the input thereto is the same value both in the upright and inverted modes of operation.
Claim 4
Dependent Claim
14 words
The detector circuit of claim 1 wherein said inverter means is an operational amplifier.
Claim 5
Dependent Claim
15 words
The detector circuit of claim 1 wherein said switching means are field effect transistors (FET).
Claim 6
Dependent Claim
17 words
The detector circuit of claim 4 wherein one of said FET switches is of a P-channel type.
Claim 7
Dependent Claim
17 words
The detector circuit of claim 4 wherein one of said FET switches is of a N-channel type.
Claim 8
Dependent Claim
18 words
The detector circuit of claim 1 wherein said representative value is equal to that of said reference voltage.
Claim 9
Dependent Claim
17 words
The detector circuit of claim 7 wherein said reference voltage is set by appropriatedly valued resistive elements.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-10 | 1979-05-12 | 1979-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-10 | 1983-05-12 | 1983-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-10 | 1987-05-12 | 1987-11-11 | $7700.00 | Window Closed / Lapsed |