US3919634A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current arrangement for correcting the measured voltage of an analog speed transducer
Assignee: Siemens AG
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Filing: 1974-05-13
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Granted: 1975-11-11
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Expires: 1994-05-13
Abstract
Abstract An improved circuit arrangement for correcting the measured voltage of an analog speed transducer using a correction voltage derived from the speed proportional pulse train of a digital speed transducer in which the correction voltage is formed in an integrating control whose reference value is a speed proportional pulse train made up of pulses having a constant voltage-time area and whose actual value is the corrected measured voltage. The correction voltage is then added to the voltage output of the analog speed transducer in a summing amplifier to obtain the corrected measured voltage output.
Inventors
- 👤 Horst Appel
- 👤 Klaus Bohm
- 👤 Gerhard Gleissner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:13
CPC Classifications
G; G01; G01P; G01P21/00; G01P21/02; G01P3/00; G01P3/42; G01P3/44; G01P3/46; G01P3/48; G01P3/481; G01P3/489; Y; Y10; Y10S; Y10S388/00; Y10S388/90; Y10S388/907; Y10S388/912; Y10S388/923; Y10S388/933
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
135 words
A circuit arrangement for correcting the measured voltage of an analog speed transducer comprising: a. a digital speed transducer rotating with the same speed as the analog speed transducer and providing an output which is a speed proportional pulse train; b. means to convert said speed proportional pulse train into a pulse train having the same period as said speed proportional sequence but having pulses of constant voltage-time area; c. a summing amplifier having as one input the output of the analog speed transducer and providing at its output a corrected measured voltage; and d. an integrator having as a controlled variable input the output of said summing amplifier and as a reference input said pulse train having pulses of constant voltage-time areas, and providing its output as a second input to said summing amplifier.
Claim 2
Dependent Claim
135 words
A circuit arrangement for correcting the measured voltage of an analog speed transducer comprising: a. a digital speed transducer rotating with the same speed as the analog speed transducer and providing an output which is a speed proportional pulse train; b. means to convert said speed proportional pulse train into a pulse train having the same period as said speed proportional sequence but having pulses of constant voltage-time area; c. a summing amplifier having as one input the output of the analog speed transducer and providing at its output a corrected measured voltage; and d. an integrator having as a controlled variable input the output of said summing amplifier and as a reference input said pulse train having pulses of constant voltage-time areas, and providing its output as a second input to said summing amplifier.
Claim 3
Dependent Claim
80 words
A circuit arrangement according to claim 1 wherein said means for converting said speed proportional pulse train into a pulse train having pulses of constant voltage-time area comprises: a. means for developing a pulse train with the same period as said speed proportional pulse train, made up of pulses of a constant predetermined length, b. a reference voltage; and c. switching means for coupling said reference voltage to the reference input of said integrator for the length of said pulses.
Claim 4
Dependent Claim
138 words
A circuit arrangement according to claim 2 wherein said means for developing a pulse of constant length comprise: a. a first flipflop having its set input coupled to the output of said digital speed transducer; b. a clock providing a highly accurate output frequency fo; c. an AND gate having as inputs the output of said first flipflop and the output of said clock; d. a counter having as an input the output of said AND gate; and e. means for evaluation having as inputs the outputs of predetermined stages of said counter, said means for evaluation responsive to a first predetermined count to close said switch coupling said reference voltage and to a second predetermined count to open said switch, said means further adapted to reset said first flipflop and said counter upon opening of said switch.
Claim 5
Dependent Claim
33 words
A circuit arrangement according to claim 3 wherein said second predetermined number is equal to the highest possible count of said counter whereby upon reaching said count, said counter will be automatically reset.
Claim 6
Dependent Claim
90 words
A circuit arrangement according to claim 4 wherein said means for evaluation comprise: a. a NAND gate having as inputs the outputs of each stage of said counter; and b. a second flipflop having its set input coupled to one of the outputs of said counter corresponding to said first predetermined count and having its reset input coupled to the output of said NAND gate, the output of said flipflop being coupled to said switch, and the output of said NAND gate further being coupled to reset said first flipflop.
Claim 7
Dependent Claim
14 words
A circuit arrangement according to claim 5 wherein said switch is a FET switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-10 | 1979-05-12 | 1979-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-10 | 1983-05-12 | 1983-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-10 | 1987-05-12 | 1987-11-11 | $7700.00 | Window Closed / Lapsed |