US3918045A
Expired / Lapsed
US
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Variable resolution control system
Assignee: Milacron Inc
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Filing: 1973-11-23
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Granted: 1975-11-04
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Expires: 1993-11-23
Abstract
Abstract A digital to analog converter is disclosed which produces analog signals having a phase relationship therebetween which is a function of digital input signals. The digital to analog converter is typically used in control systems for commanding or measuring the motion of a movable element. The converter contains variable modulo counters which permit a scaling of the signals during the conversion process. Consequently, input signals having different resolutions may be programmed in a control system; and the converter will produce command signals for moving the element in accordance with the input signals. Similarly, in a measuring system, the converter may be used to obtain a readout of the motion of the element according to any desired resolution.
Inventors
- 👤 Alfred Harold Morser
- 👤 Roy Gibson
- 👤 Stephen Anthony Scott
- 👤 Clifford Michael Bailey
- 👤 Ian Keith Taylor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:55
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/19; G05B19/33
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
267 words
A digital-to-analogue converter comprised in part of first and second counter circuits responsive to a source of clock pulses for producing an analogue reference signal of a constant predetermined frequency and an analogue command signal of the constant predetermined frequency, said second counter circuit including a circuit responsive to a digital input signal for changing the phase relationship of the command signal with respect to the reference signal, said phase relationship representing an analogue output signal, wherein the improvement comprises: a. means connected between the source of clock pulses and the first counter circuit for scaling the frequency of the clock pulses to produce control pulses; b. means connected to the first and second counter circuits for loading said first and second counter circuits with a first divisor signal representing a first predetermined number to cause said first and second counter circuits to produce the command and reference signals by dividing the frequency of the control pulses by the first predetermined number, said first predetermined number being chosen as a function of a predetermined resolution of the digital input signal and a predetermined electrical pitch of the analogue output signal; and c. means connected to the scaling means for loading the scaling means with a second divisor signal representing a second predetermIned number to cause the scaling means to divide the frequency of the clock pulses by the second predetermined number, said first and second predetermined numbers being chosen such that the ratio of the frequency of the clock pulses to the product of the first and second predetermined numbers is equal to the constant predetermined frequency.
Claim 2
Dependent Claim
267 words
A digital-to-analogue converter comprised in part of first and second counter circuits responsive to a source of clock pulses for producing an analogue reference signal of a constant predetermined frequency and an analogue command signal of the constant predetermined frequency, said second counter circuit including a circuit responsive to a digital input signal for changing the phase relationship of the command signal with respect to the reference signal, said phase relationship representing an analogue output signal, wherein the improvement comprises: a. means connected between the source of clock pulses and the first counter circuit for scaling the frequency of the clock pulses to produce control pulses; b. means connected to the first and second counter circuits for loading said first and second counter circuits with a first divisor signal representing a first predetermined number to cause said first and second counter circuits to produce the command and reference signals by dividing the frequency of the control pulses by the first predetermined number, said first predetermined number being chosen as a function of a predetermined resolution of the digital input signal and a predetermined electrical pitch of the analogue output signal; and c. means connected to the scaling means for loading the scaling means with a second divisor signal representing a second predetermIned number to cause the scaling means to divide the frequency of the clock pulses by the second predetermined number, said first and second predetermined numbers being chosen such that the ratio of the frequency of the clock pulses to the product of the first and second predetermined numbers is equal to the constant predetermined frequency.
Claim 3
Dependent Claim
74 words
the frequency of the clock pulses by a fourth predetermined number in response to the second gating signal to produce the second control signal, said predetermined numbers being chosen such that the ratio of the frequency of the clock pulses to the first and third predetermined numbers equals the constant predetermined frequency and the ratio of the frequency of the clock pulses to the second and fourth predetermined numbers equals the constant predetermined frequency.
Claim 4
Dependent Claim
74 words
the frequency of the clock pulses by a fourth predetermined number in response to the second gating signal to produce the second control signal, said predetermined numbers being chosen such that the ratio of the frequency of the clock pulses to the first and third predetermined numbers equals the constant predetermined frequency and the ratio of the frequency of the clock pulses to the second and fourth predetermined numbers equals the constant predetermined frequency.
Claim 5
Dependent Claim
335 words
A digital-to-analogue converter comprised in part of first and second counter circuits responsive to a source of clock pulses for producing an analogue reference signal of a constant predetermined frequency and an analogue command signal of the constant predetermined frequency, said second counter circuit including a circuit responsive to a digital input signal for changing the phase relationship of the command signal with respect to the reference signal, said phase relationship representing an analogue output signal, wherein the improvement comprises: a. means connected to the first counter circuit for loading the first counter circuit with a first divisor signal representing a first predetermined number to cause said first counter circuit to produce the reference signal by dividing the frequency of the clock pulses by said first predetermined number, said first predetermined number being chosen such that the ratio of the frequency of the clock pulses to the first predetermined number is equal to the constant predetermined frequency; b. means connected between the source of clock pulses and the second counter circuit for scaling the frequency of the clock pulses to produce a digital control signal; c. means connected to the second counter circuit for loading the second counter circuit with a second divisor signal representing a second predetermined number to cause said second counter circuit to produce the command signal by dividing the frequency of the digital control signal by the second predetermined number, said second predetermined number being chosen as a function of a predetermined resolution of the digital input signal and a predetermined electrical pitch of the analogue output signal; and d. means connected to the scaling means for loading the scaling means with a third divisor signal representing a third predetermined number to cause said scaling means to produce the digital control signal by dividing the frequency of the clock pulses by said third predetermined number, said second and third predetermined numbers being chosen such that the product of the second and third predetermined numbers is equal to the first predetermined number.
Claim 6
Dependent Claim
335 words
A digital-to-analogue converter comprised in part of first and second counter circuits responsive to a source of clock pulses for producing an analogue reference signal of a constant predetermined frequency and an analogue command signal of the constant predetermined frequency, said second counter circuit including a circuit responsive to a digital input signal for changing the phase relationship of the command signal with respect to the reference signal, said phase relationship representing an analogue output signal, wherein the improvement comprises: a. means connected to the first counter circuit for loading the first counter circuit with a first divisor signal representing a first predetermined number to cause said first counter circuit to produce the reference signal by dividing the frequency of the clock pulses by said first predetermined number, said first predetermined number being chosen such that the ratio of the frequency of the clock pulses to the first predetermined number is equal to the constant predetermined frequency; b. means connected between the source of clock pulses and the second counter circuit for scaling the frequency of the clock pulses to produce a digital control signal; c. means connected to the second counter circuit for loading the second counter circuit with a second divisor signal representing a second predetermined number to cause said second counter circuit to produce the command signal by dividing the frequency of the digital control signal by the second predetermined number, said second predetermined number being chosen as a function of a predetermined resolution of the digital input signal and a predetermined electrical pitch of the analogue output signal; and d. means connected to the scaling means for loading the scaling means with a third divisor signal representing a third predetermined number to cause said scaling means to produce the digital control signal by dividing the frequency of the clock pulses by said third predetermined number, said second and third predetermined numbers being chosen such that the product of the second and third predetermined numbers is equal to the first predetermined number.
Claim 7
Dependent Claim
99 words
a fourth divisor signal representing a fourth predetermined number in response to the second gating signal for causing the dividing means to divide the frequency of the second source of clock pulses by the fourth predetermined number to produce the second control signal, said predetermined numbers being chosen such that the ratio of the first predetermined frequency to the product of the first and third predetermined numbers is equal to the constant predetermined frequency and the ratio of the second predetermined frequency to the product of the second and fourth predetermined numbers Is equal to the constant predetermined frequency.
Claim 8
Dependent Claim
99 words
a fourth divisor signal representing a fourth predetermined number in response to the second gating signal for causing the dividing means to divide the frequency of the second source of clock pulses by the fourth predetermined number to produce the second control signal, said predetermined numbers being chosen such that the ratio of the first predetermined frequency to the product of the first and third predetermined numbers is equal to the constant predetermined frequency and the ratio of the second predetermined frequency to the product of the second and fourth predetermined numbers Is equal to the constant predetermined frequency.
Claim 9
Dependent Claim
95 words
a second divisor signal representing a second predetermined number in response to the second gating signal to cause said first and second counter circuits to produce the second reference and command signals by dividing the frequency of the second control signal by the second predetermined number, said first and second predetermined numbers being chosen as a function of the ratios of the first and second resolutions to the constant electrical pitch, respectively; and g. means responsive to the first and second gating signals and connected to the scaling means for loading the scaling means with
Claim 10
Dependent Claim
95 words
a second divisor signal representing a second predetermined number in response to the second gating signal to cause said first and second counter circuits to produce the second reference and command signals by dividing the frequency of the second control signal by the second predetermined number, said first and second predetermined numbers being chosen as a function of the ratios of the first and second resolutions to the constant electrical pitch, respectively; and g. means responsive to the first and second gating signals and connected to the scaling means for loading the scaling means with
Claim 11
Dependent Claim
74 words
the frequency of the clock pulses by a fourth predetermined number in response to the second gating signal to produce the second control signal, said predetermined numbers being chosen such that the ratio of the frequency of the clock pulses to the first and third predetermined numbers equals the constant predetermined frequency and the ratio of the frequency of the clock pulses to the second and fourth predetermined numbers equals the constant predetermined frequency.
Claim 12
Dependent Claim
74 words
the frequency of the clock pulses by a fourth predetermined number in response to the second gating signal to produce the second control signal, said predetermined numbers being chosen such that the ratio of the frequency of the clock pulses to the first and third predetermined numbers equals the constant predetermined frequency and the ratio of the frequency of the clock pulses to the second and fourth predetermined numbers equals the constant predetermined frequency.
Claim 13
Dependent Claim
94 words
the frequency of the second control signal by a second predetermined number in response to the second gating signal to produce the second command and reference signals, said first predetermined number being chosen as a function of the ratio of the first electrical pitch to the first resolution, and said second predetermined number being chosen as a function of the ratio of the second electrical pitch to the first resolution; and g. means responsive to the first and second gating signals and connected to the scaling means for causing the scaling means to divide
Claim 14
Dependent Claim
94 words
the frequency of the second control signal by a second predetermined number in response to the second gating signal to produce the second command and reference signals, said first predetermined number being chosen as a function of the ratio of the first electrical pitch to the first resolution, and said second predetermined number being chosen as a function of the ratio of the second electrical pitch to the first resolution; and g. means responsive to the first and second gating signals and connected to the scaling means for causing the scaling means to divide
Claim 15
Dependent Claim
94 words
the frequency of the second control signal by a second predetermined number in response to the second gating signal to produce the second command and reference signals, said first predetermined number being chosen as a function of the ratio of the first electrical pitch to the first resolution, and said second predetermined number being chosen as a function of the ratio of the second electrical pitch to the second resolution; and g. means responsive to the first and second gating signals and connected to the scaling means for causing the scaling means to divide
Claim 16
Dependent Claim
94 words
the frequency of the second control signal by a second predetermined number in response to the second gating signal to produce the second command and reference signals, said first predetermined number being chosen as a function of the ratio of the first electrical pitch to the first resolution, and said second predetermined number being chosen as a function of the ratio of the second electrical pitch to the second resolution; and g. means responsive to the first and second gating signals and connected to the scaling means for causing the scaling means to divide
Claim 17
Independent Claim
237 words
An apparatus selectively responsive to first and second digital input signals representing input information relative to first and second resolutions, respectively, for producing first and second analogue output signals having first and second electrical pitches and representing said input information relative thereto, the apparatus comprising: a. means for selectively supplying first and second gating signals as a function of said first and second digital input signals, respectively; b. a source of clock pulses having a predetermined frequency; c. means connected to the source of clock pulses for scaling the frequency of the clock pulses to produce first and second control signals; d. a first counter circuit responsive to the first and second control signals for producing first and second analogue reference signals having a constant predetermined frequency; e. a second counter circuit responsive to the first and second control signals and the digital input signals for producing first and second analogue command signals having the constant predetermined frequency, said second counter circuit including means for varying the phase of a command signal with respect to a corresponding reference signal in response to one of the digital input signals whereby the phase difference between the command signal and the reference signal represents one of the analogue output signals; f. means responsive to the first and second gating signals And connected to the first and second counter circuits for causing the first and second counter circuits to selectively divide
Claim 18
Independent Claim
237 words
An apparatus selectively responsive to first and second digital input signals representing input information relative to first and second resolutions, respectively, for producing first and second analogue output signals having first and second electrical pitches and representing said input information relative thereto, the apparatus comprising: a. means for selectively supplying first and second gating signals as a function of said first and second digital input signals, respectively; b. a source of clock pulses having a predetermined frequency; c. means connected to the source of clock pulses for scaling the frequency of the clock pulses to produce first and second control signals; d. a first counter circuit responsive to the first and second control signals for producing first and second analogue reference signals having a constant predetermined frequency; e. a second counter circuit responsive to the first and second control signals and the digital input signals for producing first and second analogue command signals having the constant predetermined frequency, said second counter circuit including means for varying the phase of a command signal with respect to a corresponding reference signal in response to one of the digital input signals whereby the phase difference between the command signal and the reference signal represents one of the analogue output signals; f. means responsive to the first and second gating signals And connected to the first and second counter circuits for causing the first and second counter circuits to selectively divide
Claim 19
Independent Claim
233 words
An apparatus responsive to a first digital input signal respresenting input information relative to a first resolution, for selectively producing first and second analogue output signals having first and second electrical pitches and representing said input information relative thereto, the apparatus comprising: a. means for selectively supplying first and second gating signals as a function of said first and second electrical pitches, respectively; b. a source of clock pulses having a predetermined frequency; c. means connected to the source of clock pulses for scaling the frequency of the clock pulses to produce first and second control signals; d. a first counter circuit responsive to the first and second control signals for producing first and second analogue reference signals having a constant predetermined frequency; e. a second counter circuit responsive to the first and second control signals and the digital input signals for producing first and second analogue command signals having the constant predetermined frequency, said second counter circuit including means for varying the phase of a command signal with respect to a corresponding reference signal in response to one of the digital input signals whereby the phase difference between the command signal and the reference signal represents one of the analogue output signals; f. means responsive to the first and second gating signals and connected to the first and second counter circuits for causing the first and second counter circuits to selectively divide
Claim 20
Independent Claim
233 words
An apparatus responsive to a first digital input signal respresenting input information relative to a first resolution, for selectively producing first and second analogue output signals having first and second electrical pitches and representing said input information relative thereto, the apparatus comprising: a. means for selectively supplying first and second gating signals as a function of said first and second electrical pitches, respectively; b. a source of clock pulses having a predetermined frequency; c. means connected to the source of clock pulses for scaling the frequency of the clock pulses to produce first and second control signals; d. a first counter circuit responsive to the first and second control signals for producing first and second analogue reference signals having a constant predetermined frequency; e. a second counter circuit responsive to the first and second control signals and the digital input signals for producing first and second analogue command signals having the constant predetermined frequency, said second counter circuit including means for varying the phase of a command signal with respect to a corresponding reference signal in response to one of the digital input signals whereby the phase difference between the command signal and the reference signal represents one of the analogue output signals; f. means responsive to the first and second gating signals and connected to the first and second counter circuits for causing the first and second counter circuits to selectively divide
Claim 21
Independent Claim
248 words
An apparatus selectively responsive to first and second digital input signals representing input information relative to first and second resolutions, respectively, for producing first and second analogue output signals having a constant electrical pitch and representing said input information relative to said constant electrical pitch, the apparatus comprising: a. means for selectively supplying first and second gating signals as a function of said first and second resolutions, respectively; b. first and second sources of clock pulses having first and second predetermined frequencies; c. means connected to the first and second sources of clock pulses for scaling the first and second frequencies of the clock pulses to produce first and second control signals, respectively; d. a first counter circuit responsive to the first and second control signals for selectively generating first and second analogue reference signals, respectively, having a constant predetermined frequency; e. a second counter circuit responsive to the first and second control signals and the first and second digital input signals for producing first and second analogue command signals, respectively, having the constant predetermined frequency, said second counter circuit including means for varying the phase of a command signal with respect to a corresponding reference signal in response to a digital input signal whereby said phase difference between the command and reference signals represents an analogue output signal; and f. means responsive to the first and second gating signals and connected to the first and second counter circuits for loading said first and second counter circuits with
Claim 22
Independent Claim
248 words
An apparatus selectively responsive to first and second digital input signals representing input information relative to first and second resolutions, respectively, for producing first and second analogue output signals having a constant electrical pitch and representing said input information relative to said constant electrical pitch, the apparatus comprising: a. means for selectively supplying first and second gating signals as a function of said first and second resolutions, respectively; b. first and second sources of clock pulses having first and second predetermined frequencies; c. means connected to the first and second sources of clock pulses for scaling the first and second frequencies of the clock pulses to produce first and second control signals, respectively; d. a first counter circuit responsive to the first and second control signals for selectively generating first and second analogue reference signals, respectively, having a constant predetermined frequency; e. a second counter circuit responsive to the first and second control signals and the first and second digital input signals for producing first and second analogue command signals, respectively, having the constant predetermined frequency, said second counter circuit including means for varying the phase of a command signal with respect to a corresponding reference signal in response to a digital input signal whereby said phase difference between the command and reference signals represents an analogue output signal; and f. means responsive to the first and second gating signals and connected to the first and second counter circuits for loading said first and second counter circuits with
Claim 23
Dependent Claim
383 words
A numerical control of the type responsive to a first input signal defining a first dimensional resolution with respect to inch units and a second input signal defining a second dimensional resolution with respect to metric units, said control comprised in part of a pulse generator producing first and second digital signals corresponding to the input signals, a feedback element responsive to a reference signal for producing a feedback signal of a constant predetermined frequency and having a predetermined electrical pitch representing motion of a movable element with respect to inch units and a phase discriminator circuit responsive to the feedback signal and a command signal for producing an error signal to control a drive mechanism coupled to the movable element, wherein the improvement comprises: a. a source of clock pulses; b. a first variable modulo counting means responsive to the clock pulses and the digital signals for selectively producing a first control signal in response to the first digital signal and a second control signal in response to the second digital signal; c. a second variable modulo counting means responsive to the control signals and the digital signals for selectively producing a first reference signal of the constant predetermined frequency in response to the first digital signal and a second reference signal of the constant predetermined frequency in response to the second digital signal; and d. a third variable modulo counting means responsive to the control signals and the digital signals for selectively producing a first command signal of the constant predetermined frequency in response to the first digital signal and a second command signal of the constant predetermined frequency in response to the second digital signal, said third modulo counting means including means responsive to the digital signals for changing the phase of the command signals with respect to the reference signals in response to the digital signals, said modulo numbers for the second and third counting means being chosen in response to the digital signals as a function of the ratio of the electrical pitch to the dimensional resolutions of the input signals, and said modulo number for the first counting means being chosen to maintain the frequency of the command signals and the reference signals equal to the constant predetermined frequency in response to each of the input signals.
Claim 24
Dependent Claim
383 words
A numerical control of the type responsive to a first input signal defining a first dimensional resolution with respect to inch units and a second input signal defining a second dimensional resolution with respect to metric units, said control comprised in part of a pulse generator producing first and second digital signals corresponding to the input signals, a feedback element responsive to a reference signal for producing a feedback signal of a constant predetermined frequency and having a predetermined electrical pitch representing motion of a movable element with respect to inch units and a phase discriminator circuit responsive to the feedback signal and a command signal for producing an error signal to control a drive mechanism coupled to the movable element, wherein the improvement comprises: a. a source of clock pulses; b. a first variable modulo counting means responsive to the clock pulses and the digital signals for selectively producing a first control signal in response to the first digital signal and a second control signal in response to the second digital signal; c. a second variable modulo counting means responsive to the control signals and the digital signals for selectively producing a first reference signal of the constant predetermined frequency in response to the first digital signal and a second reference signal of the constant predetermined frequency in response to the second digital signal; and d. a third variable modulo counting means responsive to the control signals and the digital signals for selectively producing a first command signal of the constant predetermined frequency in response to the first digital signal and a second command signal of the constant predetermined frequency in response to the second digital signal, said third modulo counting means including means responsive to the digital signals for changing the phase of the command signals with respect to the reference signals in response to the digital signals, said modulo numbers for the second and third counting means being chosen in response to the digital signals as a function of the ratio of the electrical pitch to the dimensional resolutions of the input signals, and said modulo number for the first counting means being chosen to maintain the frequency of the command signals and the reference signals equal to the constant predetermined frequency in response to each of the input signals.
Claim 25
Dependent Claim
38 words
The apparatus of claim 6, wherein the control further comprises a switching means for producing a first switching signal in response to the first digital signal and a second switching signal in response to the second digital signal.
Claim 26
Dependent Claim
52 words
The apparatus of claim 7, wherein the source of clock pulses further comprises: a. first means responsive to the first switching signal for supplying first clock pulses having a first predetermined frequency; and b. second means responsive to the second switching signal for supplying second clock pulses having a second predetermined frequency.
Claim 27
Dependent Claim
142 words
The apparatus of claim 8, wherein the second variable modulo counting means further comprises: a. a second counter changing state in response to each period of the control signals; b. means connected to the second counter for setting a first modulo in the second counter in response to the first switching signal and resetting the first modulo in response to a predetermined state of the second counter, said first modulo being equal to the ratio of the predetermined electrical pitch to the first dimensional resolution; and c. means connected to the second counter for setting a second modulo in the second counter in response to the second switching signal and resetting the second modulo in response to the predetermined state of the second counter, said second modulo being equal to the ratio of the predetermined electrical pitch to the second dimensional resolution.
Claim 28
Dependent Claim
146 words
The apparatus of claim 9, wherein the third variable modulo counting means further comprises: a. a third counter changing state in response to each period of the control signals, said third counter circuit further including a first counter stage responsive to the digital signals for incrementally changing the phase of a command signal with respect to a corresponding reference signal in response to the sign of a digital signal; b. means connected to the third counter for setting the first modulo in the third counter in response to the first switching signal and resetting the first modulo in response to a predetermined state of the third counter; and c. means connected to the third counter for setting the second modulo in the third counter in response to the second switching signal and resetting the second modulo in response to the predetermined state of the third counter.
Claim 29
Dependent Claim
202 words
The apparatus of claim 10, wherein the first variable modulo counting means further comprises: a. a first counter circuit being connected serially between the first supplying means and the second and third counter circuits in response to the first switching signal and between the second supplying means and the second and third counter circuits in response to the second switching signal, said counter changing state in response to each period of said clock pulses; b. means connected to the first counter circuit for setting a third modulo in the first counter in response to the first switching signal and resetting the third modulo in response to a predetermined state of said first counter, said third modulo being equal to the ratio of the first predetermined frequency to the product of the predetermined constant frequency and the first modulo; and c. means connected to the first counter for setting a fourth modulo in the first counter in response to the second switching signal and resetting the fourth modulo in response to the predetermined state of the first counter, said fourth modulo being equal to the ratio of the second predetermined frequency to the product of the predetermined constant frequency and the second modulo.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-03 | 1979-05-05 | 1979-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-03 | 1983-05-05 | 1983-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-03 | 1987-05-05 | 1987-11-04 | $7700.00 | Window Closed / Lapsed |