Thin-film semiconductor memory apparatus

Claim 2

A nonvolatile memory cell for digital data storage comprising: a pair of thin-film storage diodes connected in series opposition; means for applying a voltage of predetermined polarity above a predetermined amplitude across the pair of series-connected diodes so as to switch said diodes into opposite conductivity states; and means coupled to the junction of both of said diodes in order to provide an indication of the conductivity states of said diodes by sensing polarity of a voltage change at said junction when said diodes are switched into opposite conductivity states.

Claim 3

The nonvolatile memory cell of claim 1 wherein each of said diodes comprises a layer of gallium arsenide between a layer of tellurium and a layer of refractory metal, said refractory metal comprising one of the group consisting of molybdenum, tungsten and tantalum.

Claim 4

The nonvolatile memory cell of claim 2 wherein said means coupled to the junction of both of said diodes comprises an alloy of nickel and chromium.

Claim 5

An array for storage of digital data comprising: a plurality of memory cells, each cell including a pair of thin-film storage diodes connected in series opposition; conductive means connecting said memory cells in an array of rows and columns; means for selectively applying a voltage of predetermined polarity above a predetermined amplitude across any one of said pairs of series-connected diodes through said conductive means so as to switch the diodes of said one of said pairs into opposite conductivity states; and means coupled to the junction of both diodes of any one of said pairs in order to provide an indication of the conductivity states of the diodes in said one of said pairs by selectively sensing polarity of a voltage change at said junction when the diodes of said one of said pairs are switched into opposite conductivity states.

Claim 6

An array for storage of digital data comprising: a plurality of memory cells, each cell including a pair of thin-film storage diodes connected in series opposition; conductive means connecting said memory cells in an array of rows and columns; means for selectively applying a voltage of predetermined polarity above a predetermined amplitude across any one of said pairs of series-connected diodes through said conductive means so as to switch the diodes of said one of said pairs into opposite conductivity states; and means coupled to the junction of both diodes of any one of said pairs in order to provide an indication of the conductivity states of the diodes in said one of said pairs by selectively sensing polarity of a voltage change at said junction when the diodes of said one of said pairs are switched into opposite conductivity states.

Claim 7

The array of claim 4 wherein each of said diodes comprises a layer of refractory metal overlaying a common substrate, said refractory metal comprising one of the group consisting of molybdenum, tungsten and tantalum, a layer of gallium arsenide overlaying and in intimate contact with said refractory metal, and a layer of tellurium overlaying and in intimate contact with said layer of gallium arsenide.

Claim 8

The array of claim 4 wherein each pair of diodes in each cell comprise a common layer of refractory metal overlaying a common substrate, said refractory metal comprising one of the group consisting of molybdenum, tungsten and tantalum, a common layer of gallium arsenide overlaying and in intimate contact with said refractory metal, and first and second layers of tellurium overlaying and in intimate contact with said layer of gallium arsenide, said first and second layers of tellurium being spaced apart from each other on said layer of gallium arsenide.

Claim 9

The array of claim 6 wherein said means coupled to the junction of both diodes of said one of said pairs comprises a layer of an alloy of predetermined sheet resistance, said alloy overlaying said common substrate and being in intimate contact with said refractory metal.

Claim 10

The array of claim 7 wherein said alloy comprises nickel and chromium, said layer of alloy extending on said substrate beneath a portion of said layer of refractory metal.

Claim 11

The array of claim 7 wherein said conductive means comprises first columns of metallic strips, each of said strips of said first columns being electrically connected to said first layers of tellurium of the cells in each respective column, second columns of metallic strips spaced apart from said first columns of metallic strips, each of said strips of said second columns being electrically connected to said layer of an alloy of predetermined sheet resistance of the cells in each respective column, and a plurality of rows of metallic strips spaced apart from said first and second columns of metallic strips, each of said strips of said rows being electrically connected to said second layers of tellurium of the cells in each respective row.

Claim 12

The array of claim 9 wherein said metallic strips comprise electrically separated layers of platinum deposited on said array.

Claim 13

The array of claim 9 including circuit means for energizing said first columns of metallic strips and said plurality of rows of metallic strips, and readout means coupled to said second columns of metallic strips for providing output signals from said array.

Claim 14

The array of claim 11 including means for selectively grounding said second columns of metallic strips.