Power converter with rapid response current limiter

Claim 2

A power converter with a rapid response current limiter comprising, in combination: a. first and second switching transistors and an output transformer winding connected to provide a power converter when energized by a d.c. voltage and when said transistors are alternately switched by first and second square waves applied to their base terminals; b. a current sensing resistor connected to said converter to provide a current signal constituting a function of the current passing through said switching transistors; c. a peak current reference signal; and d. limiter means including comparator means receiving said current signal and reference signal and providing an output signal of very narrow pulse width of approximately one or two microseconds whenever said current signal exceeds the value of said reference signal; and, first and second flip-flop and associated gating means for passing said first and second square waves to said switching transistors, respectively, said flip-flops being connected to said comparator means and responsive to the presence of said output signal to close the gating means before a complete square wave can pass through the gating means to thereby truncate the width of the square waves applied to the base terminals of the switching transistors, said width being truncated at the instant that said current signal exceeds said reference signal thereby abruptly turning off said switching transistors thus limiting the absolute peak current passing through the transistors to a safe value determined by the reference signal.

Claim 3

A power converter with a rapid response current limiter comprising, in combination: a. a source of d.c. voltage; b. first and second switching transistors each having collector, emitter and base terminals; c. a transformer having primary and secondary windings, the primary winding having its opposite ends connectEd to said collector terminals respectively, said emitter terminals connecting together at a common junction point; d. a current sensing resistor connected to said junction point, said source of d.c. voltage being connected between the other end of said current sensing resistor and a center tap on said primary winding; e. first and second square wave form generating means providing first and second square waves; f. first and second driver means connected to the base terminals of said transistors respectively responsive to said first and second square waves from said generating means to alternately switch said transistors; g. first gating means connected between said first square wave generating means and said first driver means and second gating means connected between said second square wave generating means and said second driver means; h. a first flip-flop circuit connected to said first gating means and to said first square wave form generating means and a second flip-flop circuit connected to said second gating means and to said second square wave form generating means; i. a peak current reference source; and, j. comparator means having inputs connected to said peak current reference source and across said sensing resistor respectively and having an output line connected to both said first and second flip-flop circuits, the leading edge of each of said first and second square waves from the first and second square wave generating means setting said first and second flip-flop circuits respectively to set states to hold said first and second gating means open to pass said first and second square waves to the first and second driver means respectively, any current at said junction point exceeding said peak current reference actuating said comparater means to provide an output signal to both said first and second flip-flop circuits to switch them to clear states to thereby close said gating means whereby the current flow through said switching transistors is blocked from exceeding the value of said peak current reference until the next leading edge of the square waves switches the flip-flop circuits back to their set states to again open the gating means.

Claim 4

A power converter with a rapid response current limiter comprising, in combination: a. a source of d.c. voltage; b. first and second switching transistors each having collector, emitter and base terminals; c. a transformer having primary and secondary windings, the primary winding having its opposite ends connectEd to said collector terminals respectively, said emitter terminals connecting together at a common junction point; d. a current sensing resistor connected to said junction point, said source of d.c. voltage being connected between the other end of said current sensing resistor and a center tap on said primary winding; e. first and second square wave form generating means providing first and second square waves; f. first and second driver means connected to the base terminals of said transistors respectively responsive to said first and second square waves from said generating means to alternately switch said transistors; g. first gating means connected between said first square wave generating means and said first driver means and second gating means connected between said second square wave generating means and said second driver means; h. a first flip-flop circuit connected to said first gating means and to said first square wave form generating means and a second flip-flop circuit connected to said second gating means and to said second square wave form generating means; i. a peak current reference source; and, j. comparator means having inputs connected to said peak current reference source and across said sensing resistor respectively and having an output line connected to both said first and second flip-flop circuits, the leading edge of each of said first and second square waves from the first and second square wave generating means setting said first and second flip-flop circuits respectively to set states to hold said first and second gating means open to pass said first and second square waves to the first and second driver means respectively, any current at said junction point exceeding said peak current reference actuating said comparater means to provide an output signal to both said first and second flip-flop circuits to switch them to clear states to thereby close said gating means whereby the current flow through said switching transistors is blocked from exceeding the value of said peak current reference until the next leading edge of the square waves switches the flip-flop circuits back to their set states to again open the gating means.

Claim 5

The subject matter of claim 2, in which said source of d.c. voltage includes a bridge rectifier and filter connected to a 120 volt 60 cycle source, a low voltage rectifier and filter connected to said secondary winding of said transformer to provide an output d.c. current to a load, and in which said first and second square wave generating means include: a. a high frequency oscillator means; b. a flip-flop circuit connected to be switched back and forth by said oscillator means to provide first and second square waves 180* out of phase with each other at its two output sides; c. regulating means responsive to said d.c. current passed to a load for pulse width modulating said first and second square waves to provide said first and second square waves passed to said first and second gating means respectively whereby the output d.c. current to a load is regulated to a desired average current value.

Claim 6

The subject matter of claim 3, in which said regulating means includes a sensing resistor in series with the load to which said d.c. current is passed to provide a voltage level signal constituting a function of said d.c. current; a comparator having first and second inputs receiving respectively the high frequency from said oscillating means in the form of a saw tooth and said voltage level signal to provide at its output a series of square waves whose widths vary with variations in said voltage level signal; and first and second coincidence circuits receiving in first inputs said first and second square waves from said flip-flop outputs respectively and in their second inputs said series of square waves to thereby pulse width modulate said first and second square waves to effect said regulation to a desired current value.

Claim 7

The subject matter of claIm 4, in which said oscillator means includes an oscillator having its output connected to a saw tooth generator for providing the first input to said comparator, said oscillator also connecting to a square wave generator for effecting the back and forth switching of said flip-flop circuit.