US3914587A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Calculator having a memory preset key
Assignee: Boeing North American Inc
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Filing: 1974-03-29
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Granted: 1975-10-21
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Expires: 1994-03-29
Abstract
Abstract The number of control keys necessary to operate a four function calculator having a x and y and memory registers is reduced by a memory preset key.
Inventors
- 👤 Ralph W Haines
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:43
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/02; H03M11/04; H03M11/14; H03M11/18; G; G06; G06F; G06F15/00; G06F15/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
236 words
In a device which performs a plurality of operations on data, a combination comprising: a first register having respective input terminals and an output terminal; flip-flop means having first and second output terminals, said first output terminal for providing a first true signal when said flip-flop means is in a set state, said second output terminal for providing a second true signal when said flip-flop means is in a reset state, said flip-flop means being in said reset state upon completion of every operation; actuation means connected to said flip-flop means for placing said flip-flop means in said set state; operation means for selectively providing a plurality of respective third true signals; first gate means having respective inputs connected to said operation means and said first output terminal of said flipflop means, said first gate means having respective outputs connected to said respective input terminals of said first register, said first gate means for permitting entry of data into said first register upon application of one of said respective third true signals to said first gate means provided said flip-flop means is in a set state; and second gate means connected to said first output terminal of said flip-flop means and said output terminal of said first register, said second gate means for permitting transfer of data from said first register to other parts of the device provided said flip-flop means is in a set state.
Claim 2
Dependent Claim
236 words
In a device which performs a plurality of operations on data, a combination comprising: a first register having respective input terminals and an output terminal; flip-flop means having first and second output terminals, said first output terminal for providing a first true signal when said flip-flop means is in a set state, said second output terminal for providing a second true signal when said flip-flop means is in a reset state, said flip-flop means being in said reset state upon completion of every operation; actuation means connected to said flip-flop means for placing said flip-flop means in said set state; operation means for selectively providing a plurality of respective third true signals; first gate means having respective inputs connected to said operation means and said first output terminal of said flipflop means, said first gate means having respective outputs connected to said respective input terminals of said first register, said first gate means for permitting entry of data into said first register upon application of one of said respective third true signals to said first gate means provided said flip-flop means is in a set state; and second gate means connected to said first output terminal of said flip-flop means and said output terminal of said first register, said second gate means for permitting transfer of data from said first register to other parts of the device provided said flip-flop means is in a set state.
Claim 3
Dependent Claim
109 words
The combination recited in claim 1 further comprising: a second register; third gate means having respective inputs connected to said operations means and said second output terminal of said flip-flop means, said third gate means for permitting entry of data into said second register upon application of one of said respective third true signals to said third gate means provided said flip-flop means is in a reset state; and fourth gate means connected to said second output terminal of said flip-flop means, said fourth gate means for permitting transfer of data from said second register to other parts of the device provided said flip-flop is in a reset state.
Claim 4
Dependent Claim
64 words
The combination as recited in claim 2 further comprising: a third register; and fifth gate means having respective inputs connected to said operations means and said first and second output terminals of said flip-flop means, said fifth gate means for permitting entry of various data into said third register upon actuation of said operation means in accordance with the state of said flip-flop means.
Claim 5
Dependent Claim
136 words
The combination recited in claim 3 comprising an arithmetic unit for performing arithmetic operations on data in said third register and data transferred from either said first or second registers in accordance with the state of said flip-flop means; said operation means includes an addition switch, a subtraction switch, a multiplication switch, and a division switch, upon actuation of any one of said respective switches, a respective third true signal is applied to said first and fifth gate means; said first gate means then permitting the output of said arithmetic unit to be entered in said first register provided said flip-flop means is in a set state; and said fifth gate means then permitting the output of said arithmetic unit to be entered in said third register provided said flip-flop means is in a reset state.
Claim 6
Dependent Claim
83 words
The combination recited in claim 3 wherein said operation means includes a clear switch, upon actuation of said clear switch, a respective third true signal is applied to said first and fifth gate means; said first gate means then permitting said first register to be set to all zeroes provided said flip-flop means is in a set state; and said fifth gate means then permitting said third register to be set to all zeroes provided said flip-flop means is in a reset state.
Claim 7
Dependent Claim
144 words
The combination recited in claim 3 wherein said operation means includes an exchange switch, upon actuation of said exchange switch, a respective third true signal is applied to said first, third and fifth gate means; said first gate means then permitting the data in said third register to be entered in said first register provided said flip-flop means is in a set state; said third gate means then permitting the data in said third register to be entered in said second register provided said flip-flop means is in a reset state; and said fifth gate means then permitting either the data in said first register to be entered in said third register provided said flip-flop means is in a set state, or the data in said second register to be entered in said third register provided said flip-flop means is in a reset state.
Claim 8
Dependent Claim
60 words
The combination recited in claim 3 wherein said operation means includes an equals switch, upon actuation of said equals switch, a respective third true signal is applied to said fifth gate means, said fifth gate means then permitting the data in said first register to be entered in said third register provided said flip-flop means is in a set state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-20 | 1979-04-21 | 1979-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-20 | 1983-04-21 | 1983-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-20 | 1987-04-21 | 1987-10-21 | $7700.00 | Window Closed / Lapsed |