Image analyzer using a standard scanning or a multi-interlaced scanning type television system

Claim 2

An image analyzer using an interlaced scanning type television system comprising: a television circuit for converting an image to be analyzed into analog video signals; a converter circuit for converting said analog video signals into digital video signals; shift registers for storing and reading out said digital signals for respective fields, said shift registers corresponding in number to the number of said fields; a pulse supply circuit for supplying a first clock pulse for imparting a storage operation to said shift registers so that the digital signals for respective fields are successively stored in said shift registers corresponding to said reSpective fields, and for supplying a second clock pulse for imparting a read-out operation to said shift registers, after completion of said storage operation, so that said digital signals are successively read out of said shift registers in order of the horizontal scanning lines as they form one frame; a gate circuit for combining all the read-out outputs of said shift registers into one frame; and means for processing the output from said gate circuit.

Claim 3

An image analyzer according to claim 1, wherein said television circuit provides a synchronizing signal for synchronizing said supply circuit and said processing means.

Claim 4

An image analyzer according to claim 1, wherein said converter circuit compares the voltages representing said analog video signals with a suitable reference voltage and converts the former voltages into digital video signals.

Claim 5

An image analyzer using an interlaced scanning type television system comprising: a television circuit for converting an image to be analyzed into analog video signals; a converter circuit for converting said analog video signals into digital video signals; dynamic shift registers for storing and reading out said digital signals for respective fields, said dynamic shift registers corresponding in number to the number of said fields; a delay circuit associated with each of said dynamic shift registers other than that for the last field in one frame so that the content of each said dynamic shift register is re-stored upon storage operation of the dynamic shift register corresponding to the subsequent field; a pulse circuit for supplying a first clock pulse for imparting a storage operation to said dynamic shift registers so that the digital signals for respective fields are stored in said dynamic shift registers corresponding to said respective fields, and for supplying a second clock pulse for imparting a read-out operation to said dynamic shift registers, after completion of said storage operation, so that said digisignals are successively read out of said dynamic shift registers in order of the horizontal scanning lines as they form one frame; a first gate circuit connected to said converter circuit, to each of said dynamic shift registers and to each of said delay circuits so as to distribute said digital video signals for respective fields and to deliver said distributed digital video signals to said dynamic shift registers corresponding to said fields and, when one of said dynamic shift registers is in storage operation, to re-deliver the digital video signals of the other dynamic shift register which has completed its storage operation to said other dynamic shift register for storage therein; a second gate circuit connected to each of said dynamic shift register and to each of said delay circuits so as to deliver the digital signals from one of said dynamic shift registers which has completed its storage operation to said delay circuit associated with each of said dynamic shift registers until all of said dynamic shift registers complete their storage operation, and to combine the digital signals from all of said dynamic shift registers into one frame; and means for processing the output from said second gate circuit.

Claim 6

An image analyzer using an interlaced scanning type television system comprising: a television circuit for converting an image to be analyzed into analog video signals; a converter circuit for converting said analog video signals into digital video signals; dynamic shift registers for storing and reading out said digital signals for respective fields, said dynamic shift registers corresponding in number to the number of said fields; a delay circuit associated with each of said dynamic shift registers other than that for the last field in one frame so that the content of each said dynamic shift register is re-stored upon storage operation of the dynamic shift register corresponding to the subsequent field; a pulse circuit for supplying a first clock pulse for imparting a storage operation to said dynamic shift registers so that the digital signals for respective fields are stored in said dynamic shift registers corresponding to said respective fields, and for supplying a second clock pulse for imparting a read-out operation to said dynamic shift registers, after completion of said storage operation, so that said digisignals are successively read out of said dynamic shift registers in order of the horizontal scanning lines as they form one frame; a first gate circuit connected to said converter circuit, to each of said dynamic shift registers and to each of said delay circuits so as to distribute said digital video signals for respective fields and to deliver said distributed digital video signals to said dynamic shift registers corresponding to said fields and, when one of said dynamic shift registers is in storage operation, to re-deliver the digital video signals of the other dynamic shift register which has completed its storage operation to said other dynamic shift register for storage therein; a second gate circuit connected to each of said dynamic shift register and to each of said delay circuits so as to deliver the digital signals from one of said dynamic shift registers which has completed its storage operation to said delay circuit associated with each of said dynamic shift registers until all of said dynamic shift registers complete their storage operation, and to combine the digital signals from all of said dynamic shift registers into one frame; and means for processing the output from said second gate circuit.

Claim 7

An image analyzer according to claim 4, wherein said television circuit provides a synchronizing signal for synchronizing said pulse circuit and said processing means.

Claim 8

An image analyzer according to claim 4, wherein said pulse circuit provides a synchronizing signal to said first gate circuit so as to enable it to deliver new digital video signals to a first register for a new frame when the storage operation for the last field has been completed, and to said second gate circuit so as to combine the input signals thereto into one frame when the storage operation for the last field has been completed.