US3913093A
Expired / Lapsed
US
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Method of and means for transcoding binary pulses
Assignee: SCELT CENTRO STUDI E LAB TELEC
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Filing: 1974-03-04
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Granted: 1975-10-14
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Expires: 1994-03-04
Abstract
Abstract A binary pulse train is converted into a generally balanced seven-level output signal, ranging from -3 to +3, by translating each four-bit group into a pair of voltage levels representing a character in one of three alphabets, the choice of alphabet being determined by the mean voltage of the previously generated output signal. With a mean voltage of magnitude 0 or +1, a first alphabet is chosen with character unbalances ranging between 0 and +3. When the mean voltage reaches +2 or +3, a second alphabet is used whose character unbalances range between +2 and -2. If the mean voltage attains a value of +4 or +5, a third alphabet is utilized in which the character unbalance varies between 0 and 4. Half the characters of the second alphabet are identical with corresponding characters of the first alphabet; the other half are identical with corresponding characters of the third alphabet.
Inventors
- 👤 Vincentiis Girolamo De
- 👤 Renato Dogliotti
- 👤 Angelo Luvison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:50
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4919
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
254 words
A method of converting a sequence of bits into a generally balanced multilevel output signal, comprising the steps of: dividing said sequence into groups of four bits each; assigning to each possible 4-bit combination a character in each of several alphabets, any character of each alphabet representing a pair of voltage levels selected from a set of seven discrete voltage levels ranging in integral steps from a positive limit +3 through zero to a negative limit -3, the algebraic sums of the voltage levels of any character in one of said alphabets being all either zero or of a first polarity, the algebraic sums of the voltage levels of any character in another of said alphabets being all either zero or of a second polarity; generating a bipolar output signal whose voltage varies in accordance with the voltage levels represented by characters in a selected alphabet assigned to successive 4-bit groups in a bit sequence to be converted, starting with a character from said one of said alphabets; determining a mean voltage of the previously generated portion of said output signal; and selecting characters from said one of said alphabets upon said voltage lying in a near-zero range with a relatively low maximum voltage of said first polarity but selecting characters from said other of said alphabets upon said mean voltage lying in an off-zero range with a relatively high maximum voltage of said first polarity, saiD algebraic sums being so chosen as to tend to maintain said mean voltage in said near-zero range.
Claim 2
Independent Claim
254 words
A method of converting a sequence of bits into a generally balanced multilevel output signal, comprising the steps of: dividing said sequence into groups of four bits each; assigning to each possible 4-bit combination a character in each of several alphabets, any character of each alphabet representing a pair of voltage levels selected from a set of seven discrete voltage levels ranging in integral steps from a positive limit +3 through zero to a negative limit -3, the algebraic sums of the voltage levels of any character in one of said alphabets being all either zero or of a first polarity, the algebraic sums of the voltage levels of any character in another of said alphabets being all either zero or of a second polarity; generating a bipolar output signal whose voltage varies in accordance with the voltage levels represented by characters in a selected alphabet assigned to successive 4-bit groups in a bit sequence to be converted, starting with a character from said one of said alphabets; determining a mean voltage of the previously generated portion of said output signal; and selecting characters from said one of said alphabets upon said voltage lying in a near-zero range with a relatively low maximum voltage of said first polarity but selecting characters from said other of said alphabets upon said mean voltage lying in an off-zero range with a relatively high maximum voltage of said first polarity, saiD algebraic sums being so chosen as to tend to maintain said mean voltage in said near-zero range.
Claim 3
Dependent Claim
81 words
A method as defined in claim 1 wherein the highest absolute value of the algebraic sums of the voltage levels of the characters in said one of said alphabets equals the absolute value of the difference between the maximum voltage levels of said near-zero and off-zero ranges, the highest absolute value of the algebraic sums of the voltage levels of the characters in said other of said alphabets equaling the absolute value of the minimum voltage level of said off-zero range.
Claim 4
Dependent Claim
60 words
A method as defined in claim 2 wherein said alphabets include a further alphabet in which the algebraic sums of the voltage levels of the characters vary in both magnitude and polarity, a character from said further alphabet being selected upon said mean voltage lying in an intermediate range with a maximum voltage between said relatively low and high voltages.
Claim 5
Dependent Claim
64 words
A method as defined in claim 3 wherein said near-zero range encompasses the voltage levels 0 and 1, said intermediate range encompassing the voltage levels 2 and 3, said off-zero range encompassing the voltage levels 4 and 5, said algebraic sums assuming values from 0 through 4 in said near-zero and off-zero ranges and assuming values from -2 through +2 in said intermediate ranges.
Claim 6
Dependent Claim
62 words
A method as defined in claim 3 wherein said further alphabet is composed of half the characters of said one of said alphabets for the eight highest-ranking 4-bit combinations and half the characters of said other of said alphabets for the eight lowest-ranking 4-bit combinations, the characters of said one and said other of said alphabets being different for any 4-bit combination.
Claim 7
Independent Claim
274 words
A system for converting a sequence of bits into a generally balanced multi-level output signal, comprising: register means for temporarily storing successive groups of 4-bits each of a sequence to be converted; logical circuitry responsive to the bits stored in said register means for translating each 4-bit group of said sequence into a character selected from one of several alphabets, any character of each alphabet representing a pair of voltage levels selected from a set of seven discrete voltage levels ranging in integral steps from a positive limit +3 through zero to a negative limit -3, the algebraic sums of the voltage levels of any character in one of said alphabets being all either zero or of a first polarity, the algebraic sums of the voltage levels of any character in another of said alphabets being all either zero or of a second polarity; accumulator means connected to said logical circuitry for determining the mean voltage of a bipolar output signal synthesized from the selected characters; switch means in said logical circuitry for alternating between equivalent characters of different alphabets; and control means connected to said accumulator means for operating said switch means in response to said mean voltage to select characters from said one of said alphabets upon said mean voltage lying in a near-zero range with a relatively low maximum voltage of said first polarity and to select characters from said other of said alphabets upon said mean voltage lying in an off-zero range with a relatively high maximum voltage of said first polarity, said algebraic sums being so chosen as to tend to maintain said mean voltage in said near-zero range.
Claim 8
Independent Claim
274 words
A system for converting a sequence of bits into a generally balanced multi-level output signal, comprising: register means for temporarily storing successive groups of 4-bits each of a sequence to be converted; logical circuitry responsive to the bits stored in said register means for translating each 4-bit group of said sequence into a character selected from one of several alphabets, any character of each alphabet representing a pair of voltage levels selected from a set of seven discrete voltage levels ranging in integral steps from a positive limit +3 through zero to a negative limit -3, the algebraic sums of the voltage levels of any character in one of said alphabets being all either zero or of a first polarity, the algebraic sums of the voltage levels of any character in another of said alphabets being all either zero or of a second polarity; accumulator means connected to said logical circuitry for determining the mean voltage of a bipolar output signal synthesized from the selected characters; switch means in said logical circuitry for alternating between equivalent characters of different alphabets; and control means connected to said accumulator means for operating said switch means in response to said mean voltage to select characters from said one of said alphabets upon said mean voltage lying in a near-zero range with a relatively low maximum voltage of said first polarity and to select characters from said other of said alphabets upon said mean voltage lying in an off-zero range with a relatively high maximum voltage of said first polarity, said algebraic sums being so chosen as to tend to maintain said mean voltage in said near-zero range.
Claim 9
Dependent Claim
43 words
A system as defined in claim 6 wherein said logical circuitry includes gating means connected to said register means for generating said characters in binary form, and digital/analog conversion means connected to said gating means for translating the binary characters into multilevel voltages.
Claim 10
Dependent Claim
47 words
A system as defined in claim 7 wherein said switch means comprises a set of electronic switches inserted between said gating means and said conversion means, said Accumulator means being a digital accumulator connected to the output of said switch means in parallel with said conversion means.
Claim 11
Dependent Claim
140 words
A system as defined in claim 8 wherein said alphabets include a further alphabet in which the algebraic sums of the voltage levels of the characters vary in both magnitude and polarity, said further alphabet being composed of half the characters of said one of said alphabets for the eight highest-ranking 4-bit combinations and half the characters of said other of said alphabets for the eight lowest-ranking 4-bit combinations, the characters of said one and said other of said alphabets being different for any 4-bit combination, each of said switches having three operating positions for selecting characters among said one of said alphabets, said other of said alphabets and said further alphabet, a character from said further alphabet being selected upon said mean voltage lying in an intermediate range with a maximum voltage between said relatively low and high voltages.
Claim 12
Dependent Claim
47 words
A system as defined in claim 7 wherein said gating means comprises a set of networks connected through said switch means to a plurality of output leads for indicating the magnitude and to a further output lead for indicating the polarity of voltage levels constituting said characters.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-13 | 1979-04-14 | 1979-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-13 | 1983-04-14 | 1983-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-13 | 1987-04-14 | 1987-10-14 | $7700.00 | Window Closed / Lapsed |