Signal comparison circuits

Claim 2

In combination: a circuit reference point; first, second, third and fourth inverters, each having an input terminal, an output terminal and two power terminals, one power terminal of each inverter being connected to said reference point, the output terminal of the first inverter being connected to the input terminals of the second and third inverters, the output terminal of the third inverter being connected to the input terminals of the first and fourth inverters, the output terminals of the second and fourth inverters for providing circuit output signals; means for applying a first input signal to the other power terminals of the first and second inverters; and means for applying a second input signal to the other power terminals of the third and fourth inverters.

Claim 3

The combination recited in claim 1 wherein each inverter comprises: at least one transistor having a conduction path and a control electrode for controlling the conductivity of the path, said conduction path being connected between said output terminal and said one power terminal, said control electrode being connected to said input terminal; and impedance means connected between said other power terminal and said output terminal for providing a current path therebetween.

Claim 4

The combination recited in claim 2 wherein at least one of said impedance means comprises a resistor.

Claim 5

The combination recited in claim 2 wherein said impedance means in at least one of said inverters comprises a field-effect transistor having source, gate, and drain electrodes, the source and gate being connected to said other power terminal and said drain being connected to said output terminal.

Claim 6

The combination recited in claim 1 wherein at least one of said inverters comprises a pair of complementary field-effect transistors, each having source, gate, and drain electrodes, their sources being connected to separate ones of said power terminals, their gates being each connected to said input terminal and their drains each being connected to said output terminal.

Claim 7

A signal powered switching circuit for producing an output signal representative of an electrical input signal solely during the period that the electrical input signal and a control signal, which already is present when the electrical signal is applied, are both present, the output signal being derived from the electrical input signal, said circuit comprising, in combination: a common terminal and an output terminal; a first normally open switch connected between the output terminal and the common terminal; means for applying the electrical input signal to the output terminal;

Claim 8

A signal powered switching circuit for producing an output signal representative of an electrical input signal solely during the period that the electrical input signal and a control signal, which already is present when the electrical signal is applied, are both present, the output signal being derived from the electrical input signal, said circuit comprising, in combination: a common terminal and an output terminal; a first normally open switch connected between the output terminal and the common terminal; means for applying the electrical input signal to the output terminal;

Claim 9

The combination recited in claim 6 wherein the first, second and third switches comprise, respectively, first, second and third semiconductor devices, each having a conduction path with first and second terminals at the ends thereof and a control electrode for controlling the conduction thereof, the first terminal of each device being connected to the common terminal, the second terminal of the second device being connected to the control electrodes of the first and third devices, the second terminal of the third device being connected to the control electrode of the second device and the second terminal of the third device being connected to the output terminal.

Claim 10

The combination recited in claim 7 wherein the means for applying the electrical signal to the first and third switches comprises: a circuit input terminal for receiving the electrical input signal; first impedance means connected between the circuit input terminal and the second terminal of the seconD semiconductor device.

Claim 11

The combination recited in claim 7 wherein the semiconductor devices each comprise a common source connected field effect transistor.

Claim 12

The combination recited in claim 7 wherein the semiconductor devices each comprise a common emitter connected bipolar transistor.

Claim 13

The combination recited in claim 8 wherein the means for applying the control signal to the second switch comprises: a further circuit input terminal for receiving the control signal; and second impedance means connected between the further circuit input terminal and the control electrode of the second semiconductor device.

Claim 14

The combination recited in claim 8 wherein the second semiconductor device is a phototransistor and wherein the means for applying the control signal to the second switch comprises a source for producing radiation in response to the control signal and applying the radiation to the phototransistor for placing the conduction path thereof in a conductive state.

Claim 15

A signal powered switching circuit for producing an output signal which varies in accordance with variations of an electrical input signal solely during the period that the electrical input signal and an optical signal, which already is present when the electrical input signal starts, are both present, comprising, in combination: a common terminal; first and second transistors and a phototransistor, each having an emitter, a base and a collector, the emitter of each being connected to the common terminal, the collector of the first transistor being connected to the base of the phototransistor, the collector of the phototransistor being connected to the base of each of the first and second transistors; an input terminal for receiving the electrical input signal; first impedance means connected between the input terminal and the collector of the phototransistor; second impedance means connected between the input terminal and the collector of the second transistor; means for applying the optical input signal to the phototransistor; and an output terminal connected to the collector of the second transistor. second and third normally open switches; means coupling the second switch to the first and third switches for inhibiting closure of the first and third switches when the second switch is closed; means coupling the third switch to the second switch for inhibiting closure of the second switch when the third switch is closed; means for applying the electrical input signal to the first and third switches to close the first and third switches when the second switch is open; and means for applying the control signal to the second switch to close the second switch when the third switch is open.

Claim 16

A signal powered switching circuit for producing an output signal which varies in accordance with variations of an electrical input signal solely during the period that the electrical input signal and an optical signal, which already is present when the electrical input signal starts, are both present, comprising, in combination: a common terminal; first and second transistors and a phototransistor, each having an emitter, a base and a collector, the emitter of each being connected to the common terminal, the collector of the first transistor being connected to the base of the phototransistor, the collector of the phototransistor being connected to the base of each of the first and second transistors; an input terminal for receiving the electrical input signal; first impedance means connected between the input terminal and the collector of the phototransistor; second impedance means connected between the input terminal and the collector of the second transistor; means for applying the optical input signal to the phototransistor; and an output terminal connected to the collector of the second transistor. second and third normally open switches; means coupling the second switch to the first and third switches for inhibiting closure of the first and third switches when the second switch is closed; means coupling the third switch to the second switch for inhibiting closure of the second switch when the third switch is closed; means for applying the electrical input signal to the first and third switches to close the first and third switches when the second switch is open; and means for applying the control signal to the second switch to close the second switch when the third switch is open.

Claim 17

The combination recited in claim 13 further comprising: a further input terminal and a further output terminal; a further transistor having an emitter, a collector and a base connected, respectively, to the common terminal, the further output terminal and the collector of the phototransistor; third impedance means connected between the further input terminal and the collector of the phototransistor; and fourth impedance means connected between the further input terminal and the collector of the further transistor.

Claim 18

The combination recited in claim 13 further comprising: a thyristor having anode, cathode and gate terminals, said anode terminal being connected to said input terminal, said cathode terminal being connected to said common terminal and said gate terminal being connected to said output terminal for receiving said output signal; and full wave rectifier means for receiving an alternating current input signal, producing a full wave rectified direct current output signal and applying said full wave rectified output signal to said anode and cathode terminals of said thyristor.

Claim 19

The combination recited in claim 15 wherein the means for applYing the optical input signal to the phototransistor comprises a light emitting diode optically coupled to said phototransistor and responsive to a further electrical input signal for producing light and applying said light to said photoresistor.

Claim 20

The combination recited in claim 14 further comprising: a separate thyristor connected between each of the input terminals and the common terminal, each thyristor being poled in the same sense with respect to the common terminal; and a separate oppositely poled diode connected in parallel with each thyristor.