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US3909822A Expired / Lapsed US ⏱️ 0.0 years remaining

Arrangement for controlling a plurality of lamps

Assignee: AG Communication Systems Corp
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Filing: 1974-01-28
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Granted: 1975-09-30
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Expires: 1994-01-28
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Abstract

Abstract An arrangement for controlling a plurality of lamps on a time shared basis, to light individual ones of them to indicate various distinct modes of operation. The lamps are driven by lamp drivers which are individually controlled by an associated latch. The status of the lamps is stored in a memory, with the memory and the latch being simultaneously addressed and selected to control a control signal to the latch to light the lamps. A digitally generated matrix is used, and the control signals are digitally derived from a single input source. All of the control signals therefore are synchronized and the need for multiple sources is eliminated.

Inventors

  • 👤 David Q Lee
  • 👤 Dinesh K Srivastava

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 17:46
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/60; H04M3/62

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 317 words
An arrangement for individually controlling each of a plurality of lamps using a time sharing technique comprising, in combination: a. a plurality of lamps, each having a lamp driver associated with it for lighting it; b. memory means for storing the status of each of said plurality of lamps; c. status generating means for providing a plurality of control signals, each corresponding to a different mode of operation of said lamps, said status generating means driven by clock pulses from a single source and deriving a plurality of different ones of said control signals from said clock pulses, said status genreating means comprising a ground potential source for providing a steady bright control signal, a positive potential source for providing a steady dark control signal, said clock pulses being used to provide a steady dim control signal and being coupled to counter means operable to provide on one output thereof a first control signal and on another output thereof a second control signal, and gating means having said first and second control signals coupled to it for providing a wink control signal to turn on said lamps for a said period of time and to turn them off for a shorter set period of time; d. latch means coupled to each of said control drivers and operated by said contro signals to control the operation of said lamp drivers in lighting their associated lamps; e. addressing means for cyclically and sequentially addressIng said memory to read out the status of each of said plurality of lamps and for selecting the latch means associated with the addressed one of said plurality of lamps; and f. decoder means coupled to said memory means, said decoder means decoding the status of each of said addressed lamps from said memory means and selecting and coupling the signified one of said control signals to its latch means to operate said latch means.
Claim 2
Dependent Claim 317 words
An arrangement for individually controlling each of a plurality of lamps using a time sharing technique comprising, in combination: a. a plurality of lamps, each having a lamp driver associated with it for lighting it; b. memory means for storing the status of each of said plurality of lamps; c. status generating means for providing a plurality of control signals, each corresponding to a different mode of operation of said lamps, said status generating means driven by clock pulses from a single source and deriving a plurality of different ones of said control signals from said clock pulses, said status genreating means comprising a ground potential source for providing a steady bright control signal, a positive potential source for providing a steady dark control signal, said clock pulses being used to provide a steady dim control signal and being coupled to counter means operable to provide on one output thereof a first control signal and on another output thereof a second control signal, and gating means having said first and second control signals coupled to it for providing a wink control signal to turn on said lamps for a said period of time and to turn them off for a shorter set period of time; d. latch means coupled to each of said control drivers and operated by said contro signals to control the operation of said lamp drivers in lighting their associated lamps; e. addressing means for cyclically and sequentially addressIng said memory to read out the status of each of said plurality of lamps and for selecting the latch means associated with the addressed one of said plurality of lamps; and f. decoder means coupled to said memory means, said decoder means decoding the status of each of said addressed lamps from said memory means and selecting and coupling the signified one of said control signals to its latch means to operate said latch means.
Claim 3
Dependent Claim 58 words
The arrangement of claim 1, wherein said plurality of latch means are simultaneously reset at predetermined time intervals be means of a reset pulse, the time between each of said reset pulses being greater than the cycle time such that each of said latches is addressed and selected a plurality of times between each of said reset pulses.
Claim 4
Dependent Claim 190 words
The arrangement of claim 1, including two decoder means, one of said decoder means resetting each of said plurality of latch means one clock pulse before it can be set, and the other one of said decoder means decoding the status of each of said addressed lamps from said memory means and selecting and coupling the signified one of said control signals to its latch means to operate said latch means, whereby a symmetrical cyclical sequence is provided. 4. The arrangement of claim 1, wherein said addressing means comprises counter means, controller means operable to address said memory means under the control of said counter means, and a latch selector means operable to select individual ones of said latch means under the control of said counter means, said counter means being driven by clock pulses to operate said controller means to address said memory means and said latch selector means to select the corresponding one of said latch means, whereby the decoder means decodes the status of the addressed lamp from the memory means and selects and couples the signified one of the control signals to the selected latch means.
Claim 5
Dependent Claim 80 words
The arrangement of claim 4, wherein said controller means is selectively operable to address said memory means under the control of said counter means and by means of addresses supplied from a system processor,whereby said memory means can be addressed by a system processor to change the stored status of a lamp as the status of said plurality of lamp change, the status of the addressed ones of said lamps being coupled to said memory means from said system processor.
Claim 6
Dependent Claim 88 words
The arrangement of claim 1, wherein said clock pulses are 32Hz clock pulses with a 50 percent duty cycle and wherein said counter means is a divide by 16 binary counter providing 120 IPM control signals on one output thereof and 60 IPM control signals one another output thereof, said 120 IPM and said 60 IPM control signals being coupled to said gating means so as to provide a wink control signal to turn ON said lamps for 875 milliseconds and to turn them OFF for 125 milliseconds.

References Cited (Backward Citations)

US3550112A Cited
US3810150A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-09-29 1979-03-31 1979-09-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-09-29 1983-03-31 1983-09-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-09-29 1987-03-31 1987-09-30 $7700.00 Window Closed / Lapsed

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