US3909781A — Method of code conversion of messages

Claim 1

Independent Claim 156 words

An arrangement for generating a plurality of signals representing a second code from a plurality of binary coded signals of a first code, said plurality of first code signals comprising n-element address words and said plurality of second code signals comprising m-element words, said arrangement comprising: a register for the storage of signals representing nelements of an address code word of the first code; means for determining a series of m-element positions, each position adapted for receipt of a signal representing a code word element, and means for transferring each element-representing-signal from the register containing said first code word to two of said melement positions of the series of m-element positions so that with a given sequence of the n-element positions, the first nelement positions of the m-element series contain the address code word of the first code in said given sequence and the last n-element positions contain the address code word in the reversed sequence.

Claim 2

Dependent Claim 156 words

An arrangement for generating a plurality of signals representing a second code from a plurality of binary coded signals of a first code, said plurality of first code signals comprising n-element address words and said plurality of second code signals comprising m-element words, said arrangement comprising: a register for the storage of signals representing nelements of an address code word of the first code; means for determining a series of m-element positions, each position adapted for receipt of a signal representing a code word element, and means for transferring each element-representing-signal from the register containing said first code word to two of said melement positions of the series of m-element positions so that with a given sequence of the n-element positions, the first nelement positions of the m-element series contain the address code word of the first code in said given sequence and the last n-element positions contain the address code word in the reversed sequence.

Claim 3

Dependent Claim 46 words

An arrangement as claimed in claim 1, wherein it comprises an input unit comprising n outputs and a shift register comprising m stages, the n outputs of the input unit being coupled to the first n stages and the last n stages of the shift register.

Claim 4

Dependent Claim 112 words

An arrangement as claimed in claim 1, wherein the register for storing the n elements of a code word of the first code is formed by a shift register which is provided with n stages, the shift register being adapted for shifting the information contents in two possible directions, a control unit being provided for shifting the information contents over one stage in one direction a number of times in succession, followed by shifting of the information contents over one stage on the other direction, a number of times on succession one of the stages of the shift register being provided with an output for the code word of the second code.

Claim 5

Dependent Claim 85 words

An arrangement as claimed in claim 1, wherein the register for storing the n elements of a code word of the first code comprises n stages, each of the n stages being coupled, via an individual AND-gate and a common OR-gate, to an output for the code word of the second code, a control unit being provided for controlling the AND-gates such that they are first rendered suitable for the transfer of a code element in a given sequence, and subsequently in the reversed sequence.

Claim 6

Dependent Claim 149 words

An arrangement for detecting messages transmitted in accordance with a second code developed from an n-element binary first code, the elements of each code word of the first code being projected on the first n positions in given sequence and onto the last n positions in reverse sequence of an m-element second code word, where m is either 2n-1 or 2n, words of said second code being transmitted at least twice in succession without spacing, said arrangement comprising; a shift register having m stages, said shift register having an input for receiving the elements of the code words of the second code; a logic gate having inputs which are coupled to the stages of the shift register; means for integrating, said integration means responsive to the output of the logic gate; and discriminating means responsive to the integrator output for discriminating the level of the voltage of the integrator.

Claim 7

Dependent Claim 149 words

An arrangement for detecting messages transmitted in accordance with a second code developed from an n-element binary first code, the elements of each code word of the first code being projected on the first n positions in given sequence and onto the last n positions in reverse sequence of an m-element second code word, where m is either 2n-1 or 2n, words of said second code being transmitted at least twice in succession without spacing, said arrangement comprising; a shift register having m stages, said shift register having an input for receiving the elements of the code words of the second code; a logic gate having inputs which are coupled to the stages of the shift register; means for integrating, said integration means responsive to the output of the logic gate; and discriminating means responsive to the integrator output for discriminating the level of the voltage of the integrator.

Claim 8

Dependent Claim 91 words

An arrangement as claimed in claim 5 wherein the arrangement includes a counter, the output of the logic gate being coupled, via an AND-gate to said integration means and to a start input of said counter, said counter being coupled to the AND-gate and a sourcE of clock pulses, said counter being controlled by the logic gate and controlling the AND-gate such that a first output pulse of the logic gate is transferred, via the AND-gate, to said integrator means the AND-gate being subsequently blocked for a number of element periods.

Claim 9

Dependent Claim 158 words

An arrangement for detecting messages transmitted in accordance with a second code developed from an n-element binary first code, the elements of each code word of the first code being projected on the first n positions in given sequence and onto the last n positions in reverse sequence of an m-element second code word, where m is either 2n1 or 2n, words of said second code being transmitted at least twice in succession without spacing, said arrangement comprising; a shift register having n stages, said shift register having an input for receiving the elements of the code words of the second code; a first logic gate which is provided with inputs which are coupled to the stages of the shift register; a second logic gate which is provided with inputs which are coupled to the stages of the shift register; an integrator; and an AND-gate responsive to said first and second logic gates for coupling to said integrator.

Claim 10

Dependent Claim 158 words

An arrangement for detecting messages transmitted in accordance with a second code developed from an n-element binary first code, the elements of each code word of the first code being projected on the first n positions in given sequence and onto the last n positions in reverse sequence of an m-element second code word, where m is either 2n1 or 2n, words of said second code being transmitted at least twice in succession without spacing, said arrangement comprising; a shift register having n stages, said shift register having an input for receiving the elements of the code words of the second code; a first logic gate which is provided with inputs which are coupled to the stages of the shift register; a second logic gate which is provided with inputs which are coupled to the stages of the shift register; an integrator; and an AND-gate responsive to said first and second logic gates for coupling to said integrator.

Claim 11

Dependent Claim 25 words

An arrangement as claimed in claim 7, wherein the output of one of the logic gates is coupled to the AND-gate via a delay unit.

Claim 12

Dependent Claim 96 words

An arrangement as claimed in claim 7, wherein the output of one of the logic stages being coupled to a start input of a counter, the counter being coupled to the AND-gate and to a source of clock pulses, said counter being controlled by the logic gate and controlling the AND-gate such that a first output pulse of the other logic gate, appearing after a given delay after a first output pulse of the one logic gate, is transferred to the integrator via the AND-gate, the AND-gate being subsequently blocked for a number of element periods.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1978-09-29	1979-03-31	1979-09-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1982-09-29	1983-03-31	1983-09-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1986-09-29	1987-03-31	1987-09-30	$7700.00	Window Closed / Lapsed

Method of code conversion of messages

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag