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US3908155A Expired / Lapsed US ⏱️ 0.0 years remaining

Wafer circuit package

Assignee: International Business Machines Corp
•
Filing: 1974-04-19
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Granted: 1975-09-23
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Expires: 1994-04-19
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Abstract

Abstract A wafer type circuit package particularly designed for memory applications comprises a plurality of silicon wafer circuit devices disposed as an aligned stack and supported in spaced apart relationship by a plurality of electrical interconnection busses. The interconnection busses are adapted for edge connecting with electrical surfaces on the silicon wafers and with terminal contacts arranged in a base member. The terminal contacts extend through the base member and accommodate external electrical connections with other logic circuitry. A container encapsulates the wafer assembly and is hermetically sealed to the base member to retain coolant therein.

Inventors

  • 👤 Dean W Skinner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 22:05
CPC Classifications
H; H10; H10W; H10W72/00; H10W40/00; H10W40/70; H10W90/00; H10W72/834; H10W90/20; H10W90/288; H10W90/291

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 160 words
A packaging assembly for wafer-type circuit devices comprising: a. a flat base member fabricated of epoxy glass material, b. a plurality of terminal contacts arranged in a circular array in said base member and adapted for connection with external circuit means, c. a plurality of silicon circuit devices disposed as an aligned stack, d. a plurality of wafer electrical interconnection busses mounted in the terminal contacts in said base member and each including a plurality of tuning-fork type connectors adapted for edge connecting with electrical surfaces on the silicon wafers and supporting the silicon wafers in spaced apart relationship, e. a container encapsulating the wafer assembly and hermetically sealed to the base member and adapted to retain cooling fluid therein and provided with a cap in said container for introducing cooling fluid into the container, and f. an upper and a lower buss guide member having a serrated peripheral edge designed to hold the interconnection busses in spaced apart arrangement.
Claim 2
Dependent Claim 160 words
A packaging assembly for wafer-type circuit devices comprising: a. a flat base member fabricated of epoxy glass material, b. a plurality of terminal contacts arranged in a circular array in said base member and adapted for connection with external circuit means, c. a plurality of silicon circuit devices disposed as an aligned stack, d. a plurality of wafer electrical interconnection busses mounted in the terminal contacts in said base member and each including a plurality of tuning-fork type connectors adapted for edge connecting with electrical surfaces on the silicon wafers and supporting the silicon wafers in spaced apart relationship, e. a container encapsulating the wafer assembly and hermetically sealed to the base member and adapted to retain cooling fluid therein and provided with a cap in said container for introducing cooling fluid into the container, and f. an upper and a lower buss guide member having a serrated peripheral edge designed to hold the interconnection busses in spaced apart arrangement.
Claim 3
Dependent Claim 38 words
A packaging assembly for wafer-type circuit devices as defined in claim 1 and further including an assembly retainer cap member attached to the base member by bolt means and functioning to secure the assembly to the base member.

References Cited (Backward Citations)

US3648115A Cited
US3596140A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-09-22 1979-03-24 1979-09-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-09-22 1983-03-24 1983-09-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-09-22 1987-03-24 1987-09-23 $7700.00 Window Closed / Lapsed

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