US3907620A
Expired / Lapsed
US
⏱️ 0.0 years remaining
A process of forming metallization structures on semiconductor devices
Assignee: HP Inc
•
Filing: 1974-04-18
•
Granted: 1975-09-23
•
Expires: 1994-04-18
Abstract
Abstract A semiconductor device comprising a resistor formed by a region of a layer of tantalum nitride (Ta2N), said tantalum nitride layer also serving at another region as an adhesion layer and a barrier diffusion layer for the gold contacts and interconnects of the semiconductor device. A layer of tantalum nitride is also employed to form a mask for the metallization layer of a semiconductor device, the metallization layer thereafter being etched by sputter etching to produce very fine line electrical patterns for the integrated circuit.
Inventors
- 👤 Howard E Abraham
- 👤 George E Bodway
- 👤 Weldon H Jackson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:03
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10D; H10D99/00; H10P; H10P95/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
109 words
A METHOD OF FABRICATING SEMICONDUCTOR DEVICES COMPRISING THE STEPS OF FORMING A LOWER LAYER OF TA2N ON A SEMICONDUCTOR BODY, FORMING A METALLIZED LAYER OVER THE LOWER LAYER OF TA2N, FORMING AN UPPER LAYER OF TA2N OVER THE METALLIZED LAYER, FORMING A MASK ON THE UPPER SURFACE OF THE UPPER TA2N LAYER, CHEMICALLY ETCHING THE UPPER TA2N LAYER TO EXPOSE PORTIONS OF THE METALLIZED LAYER, SPUTTER ETCHING THE UPPER TA2N LAYER AND THE EXPOSED PORTIONS OF THE METALLIZED LAYER TO SIMULTANEOUSLY REMOVE THE UPPER TA2N LAYER, THE EXPOSED PORTIONS OF THE METALLIZED LAYER, AND THE PORTIONS OF THE LOWER TA2N LAYER BENEATH THE EXPOSED PORTIONS OF THE METALLIZED LAYER.
Claim 2
Independent Claim
109 words
A METHOD OF FABRICATING SEMICONDUCTOR DEVICES COMPRISING THE STEPS OF FORMING A LOWER LAYER OF TA2N ON A SEMICONDUCTOR BODY, FORMING A METALLIZED LAYER OVER THE LOWER LAYER OF TA2N, FORMING AN UPPER LAYER OF TA2N OVER THE METALLIZED LAYER, FORMING A MASK ON THE UPPER SURFACE OF THE UPPER TA2N LAYER, CHEMICALLY ETCHING THE UPPER TA2N LAYER TO EXPOSE PORTIONS OF THE METALLIZED LAYER, SPUTTER ETCHING THE UPPER TA2N LAYER AND THE EXPOSED PORTIONS OF THE METALLIZED LAYER TO SIMULTANEOUSLY REMOVE THE UPPER TA2N LAYER, THE EXPOSED PORTIONS OF THE METALLIZED LAYER, AND THE PORTIONS OF THE LOWER TA2N LAYER BENEATH THE EXPOSED PORTIONS OF THE METALLIZED LAYER.
Claim 3
Dependent Claim
39 words
A method of fabricating semiconductor devices as in claim 1 including the further step of etching away areas of the metallized layer to expose associated areas of the lower Ta2N layer to serve as resistors for the semiconductor device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-22 | 1979-03-24 | 1979-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-22 | 1983-03-24 | 1983-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-22 | 1987-03-24 | 1987-09-23 | $7700.00 | Window Closed / Lapsed |