US3906372A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for automatic frequency fine tuning in radio and television receivers
Assignee: Siemens AG
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Filing: 1974-03-20
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Granted: 1975-09-16
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Expires: 1994-03-20
Abstract
Abstract A circuit arrangement for automatic frequency fine tuning in radio and television receivers, of transmissions of different frequencies which are individually selectable by the use of respective tuning voltages, in which the fine tuning is effected with a fine tuning voltage, and upon a predetermined change in the control voltage, comprising said tuning voltages, the fine tuning voltage is cut off for a predetermined period and then reapplied.
Inventors
- 👤 Eckart Schatter
- 👤 Hans Kriedt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:39
CPC Classifications
H; H03; H03J; H03J7/00; H03J7/02; H03J7/04; H03J7/08; H03J7/12; H03J7/023
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
368 words
In a circuit arrangement for automatic frequency fine tuning, in radio and television receivers, of transmissions of different frequencies which are individually selectable by the use of respective tuning voltages, comprising a voltage supply circuit operable to selectively provide respective tuning voltages to the tunable transmission-selecting circuit of such a receiver, a voltage supply circuit operable to provide a fine tuning voltage derived from a received transmission, means to which said fine tuning voltage is supplied, operatively disposed in the said first-mentioned supply circuit for operatively forming the respective tuning and fine tuning voltages as a single tuning control voltage for the tunable transmission-selecting circuit of the receiver, electrical switch means disposed in said finetuning voltage supply circuit for operatively disconnecting the latter from said tunable transmission-selecting circuit of such a receiver, semiconductor control means responsive to predetermined changes in the tuning control voltage for opening said switch means to effect such disconnection upon the occurrence of such a change, said control means having an input to which said tuning control voltage is supplied, and an output from which a control voltage is supplied to said switch means, said control means comprising a differential amplifier to which said tuning control voltage is operatively conducted, first semiconductor means having its output connected to the output of said control means, operative to control the appearance of such control voltage thereat, and second semiconductor means having its input operatively connected to said output of said differential amplifier and its output connected to the input of said first semiconductor means, operative to actuate said first semiconductor means to supply said control voltage as said output upon predetermined output conditions of said differential amplifier, resulting from a voltage change in the tuning control voltage at said input, and a timing circuit operatively connected to said control means for maintaining the latter operative and thus the switch open for a predetermined period of time following such a change in the control voltage, said timing circuit being operatively connected to said first semiconductor means, operative to render the latter operative for a predetermined period of time following deactivation of said second semiconductor means at the conclusion of such a change in the tuning control voltage.
Claim 2
Dependent Claim
368 words
In a circuit arrangement for automatic frequency fine tuning, in radio and television receivers, of transmissions of different frequencies which are individually selectable by the use of respective tuning voltages, comprising a voltage supply circuit operable to selectively provide respective tuning voltages to the tunable transmission-selecting circuit of such a receiver, a voltage supply circuit operable to provide a fine tuning voltage derived from a received transmission, means to which said fine tuning voltage is supplied, operatively disposed in the said first-mentioned supply circuit for operatively forming the respective tuning and fine tuning voltages as a single tuning control voltage for the tunable transmission-selecting circuit of the receiver, electrical switch means disposed in said finetuning voltage supply circuit for operatively disconnecting the latter from said tunable transmission-selecting circuit of such a receiver, semiconductor control means responsive to predetermined changes in the tuning control voltage for opening said switch means to effect such disconnection upon the occurrence of such a change, said control means having an input to which said tuning control voltage is supplied, and an output from which a control voltage is supplied to said switch means, said control means comprising a differential amplifier to which said tuning control voltage is operatively conducted, first semiconductor means having its output connected to the output of said control means, operative to control the appearance of such control voltage thereat, and second semiconductor means having its input operatively connected to said output of said differential amplifier and its output connected to the input of said first semiconductor means, operative to actuate said first semiconductor means to supply said control voltage as said output upon predetermined output conditions of said differential amplifier, resulting from a voltage change in the tuning control voltage at said input, and a timing circuit operatively connected to said control means for maintaining the latter operative and thus the switch open for a predetermined period of time following such a change in the control voltage, said timing circuit being operatively connected to said first semiconductor means, operative to render the latter operative for a predetermined period of time following deactivation of said second semiconductor means at the conclusion of such a change in the tuning control voltage.
Claim 3
Dependent Claim
180 words
A circuit arrangement according to claim 1 wherein said differential amplifier comprises two npn-transistors, the emitters of which are operatively connected in common to a reference potential, the collector of the first tranSistor being connected over the collector-emitter path of a third transistor of pnp type, and the collector of the second transistor being connected over the collector-emitter path of a fourth transistor of pnp type, to supply potential, with the bases of the third and fourth transistors being connected to the emitter of a fifth transistor of pnp type, the base of which is connected to the base of the fourth transistor, and whose collector is connected to reference potential, the base of the second transistor being connected over a resistor to the input and over a resistor to a potential point, lower than the supply potential, and which is connected over a resistance to reference potential, to which point is also connected the base of the first transistor over a resistor, and the collector of the first transistor being connected to the input of said second semiconductor means.
Claim 4
Dependent Claim
95 words
A circuit arrangement according to claim 2, wherein the base of said second transistor is connected to the emitter of a sixth transistor of npn type, the base of which is connected to said lower potential point and its collector to supply potential, and a seventh transistor of pnp type, the base of which is connected to said lower potential point, its emitter to the base of said second transistor, and its collector to reference potential, said sixth and seventh transistors providing a limiting action on input voltages at the base of said second transistor.
Claim 5
Dependent Claim
77 words
A circuit arrangement according to claim 2, wherein the resistance connecting said lower potential point to reference potential comprises a first transistor of npn type, the emitter of which is connected to reference potential and the collector of which is connected to said lower potential point, the base of said first transistor being connected to the emitter of a second transistor of npn type, the base and collector of which are connected to said lower potential point.
Claim 6
Dependent Claim
84 words
A circuit arrangement according to claim 1, wherein said first semiconductor means comprises a first transistor of pnp type, the base of which forms the input of such semiconductor means, the emitter of said first transistor being connected to supply potential and the collector thereof being connected to the base of a second transistor of npn type, with the emitter being connected over a resistor to the output of said control means, and the collector of said second transistor being connected to supply potential.
Claim 7
Dependent Claim
65 words
A circuit arrangement according to claim 5, wherein the collector of said first transistor is connected to the base of said second transistor over a resistor, and a third transistor of npn type, the base of which is connected to the collector of said first transistor, the emitter of which is connected to the base of said second transistor and its collector to supply potential.
Claim 8
Dependent Claim
43 words
A circuit arrangement according to claim 6, wherein said timing means comprises a capacitor and a resistor, connected in parallel, one side of which is connected over a resistor to the base of said second transistor, and the other side to reference potential.
Claim 9
Dependent Claim
136 words
A circuit arrangement according to claim 1, wherein said second semiconductor means comprises two transistors of different types, the emitters of which are connected in common to the output of the differential amplifier, and the bases of which are connected in common to a potential point intermediate said supply potential and said lower potential, the collector of the first ransistor of npn type being connected to the input of the first semiconductor means and over a resistor to supply potential, the collector of the second transistor of pnp type being connected to reference potential over a resistor and directly to the base of a third transistor of npn type, the emitter of which is connected to reference potential and the collector of which is connected over a resistor to the input of said first semiconductor means.
Claim 10
Dependent Claim
84 words
A circuit arrangement according to claim 2, wherein said first semiconductor means compriseS a first transistor of pnp type, the base of which forms the input of such semiconductor means, the emitter of said first transistor being connected to supply potential and the collector thereof being connected to the base of a second transistor of npn type, with the emitter being connected over a resistor to the output of said control means, and the collector of said second transistor being connected to supply potential.
Claim 11
Dependent Claim
76 words
A circuit arrangement according to claim 9, wherein the collector of said first transistor of the first semiconductor means is connected to the base of the second transistor thereof over a resistor, and a third transistor of npn type, the base of which is connected to the collector of the first transistor of said semiconductor means, the emitter of which is connected to the base of the second transistor thereof and its collector to supply potential.
Claim 12
Dependent Claim
48 words
A circuit arrangement according to claim 6, wherein said timing means comprises a capacitor and a resistor connected in parallel, one side of which is connected over a resistor to the base of the second transistor of said first semiconductor means, and the other side to reference potential.
Claim 13
Dependent Claim
151 words
A circuit arrangement according to claim 10, wherein said second semiconductor means comprises two transistors of different types, the emitters of which are connected in common to the output of the differential amplifier, and the bases of which are connected in common to a potential point intermediate said supply potential and said lower potential, the collector of the first transistor of said second semiconductor means, of npn type, being connected to the input of the first semiconductor means thereof and over a resistor to supply potential, the collector of the second transistor thereof, of pnp type, being connected to reference potential over a resistor and directly to the base of a third transistor of said second semiconductor means, of npn type, the emitter of which is connected to reference potential and the collector of which is connected over a resistor to the base of the transistor of said first semiconductor means.
Claim 14
Dependent Claim
112 words
A circuit arrangement according to claim 12, wherein the base forming a part thereof of said second transistor of the differential amplifier is connected to the emitter of the sixth transistor, of the npn type, the base of which is connected to said lower potential point and its collector to supply potential, and a seventh transistor, forming a part thereof, of pnp type, the base of which is connected to said lower potential point, its emitter to the base of said second transistor of the differential amplifier, and its collector to reference potential, said sixth and seventh transistors providing a limiting action on input voltages at the base of said second transistor.
Claim 15
Dependent Claim
85 words
A circuit arrangement according to claim 13, wherein the resistance connecting said lower potential point to reference potential comprises a first further transistor of npn type, the emitter of which is connected to reference potential and the collector of which is connected to said lower potential point, the base of said first further transistor being connected to the emitter of a second further transistor of npn type, the base and collector of which are connected to said lower potential point, thereby providing potential stabilization thereat.
Claim 16
Dependent Claim
42 words
A circuit arrangement according to claim 14, wherein said intermediate potential point is connected to said supply potential and to the lower potential point by respective resistors which with said first further transistor form a voltage divider between supply and reference potentials.
Claim 17
Dependent Claim
48 words
A circuit arrangement according to claim 15, wherein said timing means comprises a capacitor and a resistor, connected in parallel, one side of which is connected over a resistor to the base of the second transistor of said first semiconductor means, and the other side to reference potential.
References Cited (Backward Citations)
US3806817A
Cited
US3743944A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |