Protective apparatus for digital logic circuits

Claim 2

Digital logic signal output apparatus which is protected against externally applied voltages substantially outside of digital logic levels, said apparatus comprising: an output terminal; an SCR, the anode of said SCR being connected to said output terminal; means for continuously applying a substantially constant bias current to the cathode of said SCR; and a digital logic circuit means for applying a digital logic signal at either of a pair of preselected logic voltage levels to the gate of said SCR, said logic level signals being transferred from the gate to the anode of said SCR with the anode operating as a non-linear current source or sink at either digital logic level, the output current value being limited for voltages substantially outside said digital logic range, the excess voltage appearing essentially across said SCR.

Claim 3

Apparatus as set forth in claim 1 wherein the cathode of said SCR is connected to the collector of an NPN transistor which is operated as a substantially constant current source.

Claim 4

Apparatus as set forth in claim 1 further comprising comparator means for determining when the voltage on said output terminal passes substantially outside digital logic levels, said current applying means being controlled by said comparator means.

Claim 5

Apparatus as set forth in claim 3 wherein said comparator means comprises an exclusive NOR gate.

Claim 6

Apparatus as set forth in claim 4 wherein said gate is a C-MOS integrated circuit.

Claim 7

Digital logic signal interfacing apparatus which protects against externally applied voltages substantially outside of digital logic levels, said apparatus comprising: an output terminal; an SCR, the anode of said SCR being connected to said output terminal; a digital logic circuit means coupled for applying digital logic level signals at either of a pair of preselected logic voltage levels to the gate of said SCR, said digital logic level signals being transferred from the gate to the anode of said SCR with the anode operating as a non-linear current source or sink at either digital logic level; sensing means responsive to voltages, at said terminal, substantially outside the normal range of digital logic levels; and source means for selectively applying a continuous substantially constant bias current at relatively high source impedance to the cathode of said SCR, said source means being controlled by said sensing means to terminate said constant current when the voltage at said terminal exceeds said normal range.

Claim 8

Digital logic signal interfacing apparatus which protects against externally applied voltages substantially outside of digital logic levels, said apparatus comprising: an output terminal; an SCR, the anode of said SCR being connected to said output terminal; a digital logic circuit means coupled for applying digital logic level signals at either of a pair of preselected logic voltage levels to the gate of said SCR, said digital logic level signals being transferred from the gate to the anode of said SCR with the anode operating as a non-linear current source or sink at either digital logic level; sensing means responsive to voltages, at said terminal, substantially outside the normal range of digital logic levels; and source means for selectively applying a continuous substantially constant bias current at relatively high source impedance to the cathode of said SCR, said source means being controlled by said sensing means to terminate said constant current when the voltage at said terminal exceeds said normal range.

Claim 9

Apparatus as set forth in claim 6 wherein said source means is controLled by a C-MOS exclusive NOR gate.

Claim 10

Apparatus for protecting an input circuit of a digital logic circuit against externally applied voltages substantially outside the range of permissible input voltages for the device, said apparatus comprising: an input terminal; an SCR, the anode of said SCR being connected to said input terminal; means connecting the gate of said SCR to the input circuit of the digital logic device, said means together with the input circuit providing a relatively low impedance load to said gate; and means for continuously applying a substantially constant bias current at relatively high source impedance to the cathode of said SCR, whereby the input current applied to said input circuit is limited to a substantially predetermined value, the excess of input voltages over said range of permissible voltages appearing across said SCR.

Claim 11

Apparatus for protecting an input circuit of a digital logic circuit against externally applied voltages substantially outside the range of permissible input voltages for the device, said apparatus comprising: an input terminal; an SCR, the anode of said SCR being connected to said input terminal; means connecting the gate of said SCR to the input circuit of the digital logic device, said means together with the input circuit providing a relatively low impedance load to said gate; and means for continuously applying a substantially constant bias current at relatively high source impedance to the cathode of said SCR, whereby the input current applied to said input circuit is limited to a substantially predetermined value, the excess of input voltages over said range of permissible voltages appearing across said SCR.

Claim 12

Apparatus as set forth in claim 8 wherein the cathode of said SCR is connected to the collector of an NPN transistor interconnected in a circuit as a substantially constant current source.

Claim 13

Protective interfacing apparatus for digital logic signal circuits, said apparatus comprising: an externally accessible terminal; a digital logic integrated circuit; a four-layer PNPN semiconductor device having a first lead at the P-type end, a second lead at the N-type end and a third lead connected to the intermediate P-type layer adjacent the N-type end; means connecting said first lead to said externally accessible terminal; means connecting said third lead to said digital logic integrated circuit; means for continuously providing through said second lead a substantially constant bias current which is substantially smaller than the digital logic level currents employed with said integrated circuit, whereby digital logic level signals are communicated between said terminal and said integrated circuit through said device but externally applied voltages substantially outside of digital logic levels appear across said device rather than being applied to said integrated circuit.

Claim 14

Protective interfacing apparatus for digital logic signal circuits, said apparatus comprising: an externally accessible terminal; a digital logic integrated circuit; a four-layer PNPN semiconductor device having a first lead at the P-type end, a second lead at the N-type end and a third lead connected to the intermediate P-type layer adjacent the N-type end; means connecting said first lead to said externally accessible terminal; means connecting said third lead to said digital logic integrated circuit; means for continuously providing through said second lead a substantially constant bias current which is substantially smaller than the digital logic level currents employed with said integrated circuit, whereby digital logic level signals are communicated between said terminal and said integrated circuit through said device but externally applied voltages substantially outside of digital logic levels appear across said device rather than being applied to said integrated circuit.