Abstract A logic equivalence gate compares signals supplied to and received from an electronic switching circuit to produce an output signal when the switching circuit fails to perform a specified switching operation. A pulse width discriminator rejects noise normally present in the output signal caused by the inherent delay of the switching circuit in normal operation. The noise free output of the pulse width discriminator is applied to a flip flop to provide a stored indication of failure of the switching circuit. The stored signal is also applied to an inhibit gate connected to the input of the switching circuit for preventing further application of input signals to the switching circuit after failure has been detected.
In combination: first means responsive to a first circuit input signal and a priming signal for producing a circuit output signal in accordance with the first circuit input signal when the priming signal is present, the circuit output signal being of a fixed value otherwise; second means responsive to a second circuit input signal and a further signal for producing an output signal in accordance with the exclusive logical sum thereof; third means responsive to a selected value of the output signal of the second means of greater than a given duration for producing a trigger signal; bistable means, initially in a first logic state for producing the priming signal and responsive to the trigger signal for switching to its second logic state for terminating the priming signal; and wherein said further signal is a selected one of the first circuit input and the circuit output signals.
Claim 2
Dependent Claim
147 words
In combination: first means responsive to a first circuit input signal and a priming signal for producing a circuit output signal in accordance with the first circuit input signal when the priming signal is present, the circuit output signal being of a fixed value otherwise; second means responsive to a second circuit input signal and a further signal for producing an output signal in accordance with the exclusive logical sum thereof; third means responsive to a selected value of the output signal of the second means of greater than a given duration for producing a trigger signal; bistable means, initially in a first logic state for producing the priming signal and responsive to the trigger signal for switching to its second logic state for terminating the priming signal; and wherein said further signal is a selected one of the first circuit input and the circuit output signals.
Claim 3
Dependent Claim
15 words
The combination recited in claim 1 wherein said second means is an EXCLUSIVE NOR gate.
Claim 4
Dependent Claim
15 words
The combination recited in claim 1 wherein said second means is an EXCLUSIVE OR gate.
Claim 5
Dependent Claim
15 words
The combination recited in claim 1 wherein said further signal is said circuit output signal.
Claim 6
Dependent Claim
16 words
The combination recited in claim 1 wherein said further signal is said first circuit input signal.
Claim 7
Dependent Claim
25 words
The combination recited in claim 1 wherein said third means comprises a low pass filter having a time constant of greater than said given duration.