US3906194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal processor
Assignee: Xerox Corp
•
Filing: 1973-12-20
•
Granted: 1975-09-16
•
Expires: 1993-12-20
Abstract
Abstract A processor for converting signals generated by a shaft encoder into two separate pulse trains. The state of the output of the encoder is loaded into a register, whose output is used as an address to a memory device. Control information is stored in the memory device in accordance with a predetermined relationship between given addresses and output signals to be generated from the memory device. Respective output signals are generated upon the memory device being accessed by a given address. In the preferred embodiment, two sets of such signals are generated by the use of two shaft encoders, orthogonal to one another within a display-oriented pointing device, for representing the Cartesian coordinates of motion of the pointing device. The state of the output of the additional shaft encoder is also loaded into the register, with an additional register connected to the output of this first register for providing additional address bits used in accessing the memory device. Two sets of output pulse trains are thereby generated from the memory device, each of which consists of two separate pulse trains. Such pulse trains are utilized to provide cursor control signals to a display monitor.
Inventors
- 👤 Douglas G Fairbairn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:53
CPC Classifications
G; G06; G06K; G06K15/00; G06K15/22; H; H03; H03M; H03M1/00; H03M1/12; H03M1/22; H03M1/24; H03M1/28; H03M1/30
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
256 words
A processor for converting two sets of signals from a pair of shaft encoders, each set of which comprises a pair of signals approximately 90* out of phase with one another, into two binary pulse trains respective to each encoder, comprising: first register means for storing the state of said encoder signals for a given period of time, said encoder signals respectively representing the X and Y positional coordinates of an indicator device, second register means responsive to the output of said first register means for storing its output state during the same period of time, clocking means connected to said first register means for loading the new state of said encoder signals into said first register means and for loading the output of said first register means representing the previous state of said encoder signals into said second register means each clock cycle, and memory means responsive to the output states of said first and second register means for processing said states, said memory means storing binary values which are accessed by the outputs of said register means whereupon said memory means is addressed in parallel by both the new and previous states of said encoder signals as represented by the outputs of said first and second register means to provide binary output signals in accordance with the binary values accessed indicative of the transitions in the states of said encoder signals, said binary signals being indicative of the position of said indicator device and capable of providing cursor control signals to a display monitor.
Claim 2
Dependent Claim
256 words
A processor for converting two sets of signals from a pair of shaft encoders, each set of which comprises a pair of signals approximately 90* out of phase with one another, into two binary pulse trains respective to each encoder, comprising: first register means for storing the state of said encoder signals for a given period of time, said encoder signals respectively representing the X and Y positional coordinates of an indicator device, second register means responsive to the output of said first register means for storing its output state during the same period of time, clocking means connected to said first register means for loading the new state of said encoder signals into said first register means and for loading the output of said first register means representing the previous state of said encoder signals into said second register means each clock cycle, and memory means responsive to the output states of said first and second register means for processing said states, said memory means storing binary values which are accessed by the outputs of said register means whereupon said memory means is addressed in parallel by both the new and previous states of said encoder signals as represented by the outputs of said first and second register means to provide binary output signals in accordance with the binary values accessed indicative of the transitions in the states of said encoder signals, said binary signals being indicative of the position of said indicator device and capable of providing cursor control signals to a display monitor.
Claim 3
Dependent Claim
30 words
The processor of claim 1 wherein is further included counting means responsive to the output signals of said memory means for counting said transitions and providing binary signals indicative thereof.
Claim 4
Dependent Claim
103 words
The processor of claim 2 wherein the state of said encoder signals at any given instant of time are represented by four binary digits respective to each signal, wherein the previous state of said encoder signals is represented by A0, A1, A2, and A3 and the new state of said encoder signals is represented by A4, A5, A6, and A7 and where said memory means when addressed by A0, A1, A2, A3, A4, A5, A6, and A7 processes the adjacent states defined in accordance with the following logic equations which define the output signals 01, 02, 03, and 04 of said memory means:
Claim 5
Dependent Claim
13 words
The processor of claim 3 wherein said memory means is a read-only memory.
Claim 6
Dependent Claim
312 words
A processor for converting two sets of signals from a pair of shaft encoders, each set of which comprises a pair of signals approximately 90* out of phase with one another, into two binary pulse trains respective to each encoder, comprising: first register means for storing the state of said encoder signals for a given period of time, second register means responsive to the output of said first register means for storing its output state during the same period of time, clocking means connected to said first register means for loading the new state of said encoder signals into said first register means and for loading the output of said first register means representing the previous state of said encoder signals into said second register means each clock cycle, memory means responsive to the output states of said first and second register means for processing said states, said memory means storing binary values which are accessed by the outputs of said register means whereupon said memory means is addressed in parallel by both the new and previous states of said encoder signals as represented by the outputs of said first and second register means to provide binary output signals in accordance with the binary values accessed indicative of the transitions in the states of said encoder signals, the state of said encoder signals at any given instant of time being represented by four binary digits respective to each signal, the previous state of said encoder signals being represented by A0, A1, A2, and A3, and the new state of said encoder signals being represented by A4, A5, A6, and A7, and said memory means when addressed by A0, A1, A2, A3, A4, A5, A6, and A7 processes the adjacent states defined in accordance with the following logic equations which define the output signals 01, 02, 03, and 04 of said memory means:
Claim 7
Dependent Claim
312 words
A processor for converting two sets of signals from a pair of shaft encoders, each set of which comprises a pair of signals approximately 90* out of phase with one another, into two binary pulse trains respective to each encoder, comprising: first register means for storing the state of said encoder signals for a given period of time, second register means responsive to the output of said first register means for storing its output state during the same period of time, clocking means connected to said first register means for loading the new state of said encoder signals into said first register means and for loading the output of said first register means representing the previous state of said encoder signals into said second register means each clock cycle, memory means responsive to the output states of said first and second register means for processing said states, said memory means storing binary values which are accessed by the outputs of said register means whereupon said memory means is addressed in parallel by both the new and previous states of said encoder signals as represented by the outputs of said first and second register means to provide binary output signals in accordance with the binary values accessed indicative of the transitions in the states of said encoder signals, the state of said encoder signals at any given instant of time being represented by four binary digits respective to each signal, the previous state of said encoder signals being represented by A0, A1, A2, and A3, and the new state of said encoder signals being represented by A4, A5, A6, and A7, and said memory means when addressed by A0, A1, A2, A3, A4, A5, A6, and A7 processes the adjacent states defined in accordance with the following logic equations which define the output signals 01, 02, 03, and 04 of said memory means:
Claim 8
Dependent Claim
38 words
The processor of claim 5 wherein the rotation of said shaft encoders represent respectively the X and Y positional coordinates of an indicator device and wherein said binary signals are indicative of the position of said indicator device.
Claim 9
Dependent Claim
30 words
The processor of claim 6 wherein is further included counting means responsIve to the output signals of said memory means for counting said transitions and providing binary signals indicative thereof.
Claim 10
Dependent Claim
13 words
The processor of claim 7 wherein said memory means is a read-only memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |