Digital echo suppressor

Claim 2

In a communication system having means for interconnecting a two-wire circuit to a four-wire circuit wherein said four-wire circuit comprises separate two-wire paths for transmission and reception of signals and includes a voice-operated switch in each path for normally open circuiting each of said paths, a digital echo suppressor comprising: first means for comparing outgoing signals with incoming signals, said first means producing a signal of first logical significance when said outgoing signals are of greater amplitude than said incoming signals and producing a signal of second logical significance when said outgoing signals are of lesser amplitude than said incoming signals; second means responsive to said signal of second logical significance for establishing a first condition wherein said voice-operated switch in said transmission path is precluded from enabling said transmission path; third means responsive to said signal of first logical significance and to said incoming and said outgoing signals for establishing a second condition wherein said voice-operated switch in said transmission path is not precluded from enabling said transmission path and a predetermined impedance is inserted in said two-wire reception path; and fourth means for maintaining said second condition for a predetermined time interval after said first output signal terminates.

Claim 3

In a delta modulation communication system including an encoder and voice-operated switch in a transmission path and a decoder and voice-operated switch in a reception path, a digital echo suppressor comprising: first means connected to monitor activity in said encoder and to provide a first digital word representative of activity in said transmission path; second means for comparing said first digital word to a digital threshold level and for producing an output signal of first logical significance when said first digital word is smaller than said threshold level and for producing an output signal of second logical significance when said first digital word is larger than said threshold level; third means connected to monitor activity in said decoder and to provide a second digital word representative of activity in said reception path; fourth means connected to receive said second digital word and for selecting the largest of said second digital words detected during a first predetermined time period; fifth means connected to receive and store said largest of said second digital words for a second predetermined time peeriod; sixth means connected to receive and compare said first digital word and said largest of said second digital words, said sixth means providing an output signal of first logical significance when said first digital word is smaller than said largest of said second digital words and providing an output signal of second logical significance when said first digital word is larger than said largest of said second digital words; seventh means connected to receive said output signals from said sixth means, said seventh means being responsive to said signal of first logical significance to inhibit said voice-operated switch in the transmission path from enabling said transmission path and being responsive to said signal of second logic significance to remove said inhibit.

Claim 4

In a delta modulation communication system including an encoder and voice-operated switch in a transmission path and a decoder and voice-operated switch in a reception path, a digital echo suppressor comprising: first means connected to monitor activity in said encoder and to provide a first digital word representative of activity in said transmission path; second means for comparing said first digital word to a digital threshold level and for producing an output signal of first logical significance when said first digital word is smaller than said threshold level and for producing an output signal of second logical significance when said first digital word is larger than said threshold level; third means connected to monitor activity in said decoder and to provide a second digital word representative of activity in said reception path; fourth means connected to receive said second digital word and for selecting the largest of said second digital words detected during a first predetermined time period; fifth means connected to receive and store said largest of said second digital words for a second predetermined time peeriod; sixth means connected to receive and compare said first digital word and said largest of said second digital words, said sixth means providing an output signal of first logical significance when said first digital word is smaller than said largest of said second digital words and providing an output signal of second logical significance when said first digital word is larger than said largest of said second digital words; seventh means connected to receive said output signals from said sixth means, said seventh means being responsive to said signal of first logical significance to inhibit said voice-operated switch in the transmission path from enabling said transmission path and being responsive to said signal of second logic significance to remove said inhibit.

Claim 5

The improved echo suppressor as defined in claim 2 and including eighth means for inhibiting said echo suppressor operation when communication activity is preseNt in both said transmission path and said reception path.

Claim 6

The echo suppressor as defined in claim 2 wherein said fourth means comprises: a first steering logic circuit having first, second and third input terminals and an output terminal, said first input terminal of said first logic circuit being connected to receive said second digital word; a first recirculating shift register for storing a third digital word representing the largest of said second digital words detected during a first predetermined time period, said first register having an input terminal and an output terminal, said output terminal of said first register being connected to said second input terminal of said first logic circuit, said output terminal of said first logic circuit being connected to said input terminal of said first register; a first comparator having first and second input terminals and an output terminal, said first input terminal of said first comparator being connected to receive said second digital word and said second input terminal of said first comparator being connected to said output terminal of said first register, said output terminal of said first comparator being connected to said third input terminal of said first logic circuit, said first comparator producing an output signal of first logical significance when said second digital word is smaller than said third digital word and producing an output signal of second logical significance when said second digital word is larger than said third digital word; and wherein said first logic circuit is responsive to said signal of second logical significance to transfer said second digital word into said first register and is responsive to said signal of a first logical significance to cause said third digital word to be recirculated.

Claim 7

The echo suppressor as defined in claim 4 wherein said fifth means comprises: a second recirculating shift register having an input terminal and an output terminal; a second steering logic circuit having an output terminal and first, second and third input terminals, said output terminal of said second logic circuit being connected to said input terminal of said second register, said first input terminal of said second logic circuit being connected to said output terminal of said second register and said second input terminal being connected to said output terminal of said first register; a second comparator connected to compare said second digital word and said third digital word, said comparator connected to supply a signal to said second steering logic circuit to cause said second digital word to be transferred into said second register when said second digital word is larger than said third digital word; and means for supplying a periodic update signal to said third input terminal of said second logic circuit to cause said third digital word to be transferred from said first register into said second register.

Claim 8

The echo suppressor as defined in claim 5 wherein said sixth means comprises a third comparator.

Claim 9

The echo suppressor as defined in claim 6 wherein said seventh means comprises a first logic gate having a first input terminal connected to receive said signal from said comparator and a second input terminal connected to receive an enable signal from said voice-operated switch in said transmission path, and wherein said first logic gate is responsive to said signal of first logical significance to inhibit said enable signal.

Claim 10

The echo suppressor as defined in claim 7 wherein said eighth means comprises: a second logic gate having first, second and third input terminals and an output terminal, said first input terminal being connected to receive said output signal from said third comparator, said second input terminal being connected to receive said output signal from said second means, and said third input terminal being connected to receive said enable signal from said seventh means, said logic gating providing an ouTput signal of first logical significance upon simultaneous receipt of input signals of second logical significance on each of said input terminals; a counter having a clock terminal, a reset terminal and an output terminal, said counter being connected to receive said clock pulses on said clock terminal and being responsive thereto to provide an output signal at said output terminal after receipt of a predetermined number of said clock pulses, said reset terminal being connected to said output terminal of said second logic gate wherein said counter is responsive to said signal of first logical significance from said second logic gate to be reset to terminate said output signal and to be maintained in said reset state until said signal of first logical significance on said reset terminal is terminated; a multivibrator having a clock terminal, a reset terminal and an output terminal, said reset terminal being connected to said output terminal of said counter, and said clock terminal being connected to said output terminal of said second logic gate wherein said multivibrator provides an output signal of first logical significance in response to said signal of first logical significance on said clock terminal and provides an output signal of second logical significance in response to said signal of first logical significance on said reset terminal; and a third logic gate having a first input terminal connected to receive said enable signal from said first logic gate and having a second input terminal connected to receive said output signals from said multivibrator wherein said third logic gate provides an output signal in response to said enable signal on said first input terminal or said signal on said second input terminal.

Claim 11

The echo suppressor as defined in claim 8 wherein said third logic gate includes a third input terminal connected to receive a signal for disabling said echo suppressor.